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SMH4042ASBKN データシート(PDF) 4 Page - Summit Microelectronics, Inc. |
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SMH4042ASBKN データシート(HTML) 4 Page - Summit Microelectronics, Inc. |
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4 / 28 page  4 SMH4042A 2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. GND (14) Power supply return line. Ground should be applied at the same time as early power. BD_SEL1#, BD_SEL2# (13, 12) These are active low TTL level inputs with internal pull- ups to VCC. When pulled low they indicate full board insertion. On the host side the signals should be directly tied to ground. In a “High Availability” application these inputs can be the last pins to mate with the backplane. Alternatively, they can be actively driven by the host, or be connected to switches interfaced to the board ejectors, or any combination. Regardless, both inputs must be low before the SMH4042A will begin to turn on the backend voltage. DRVREN# (2) An open-drain, active-low output that indicates the status of the 3 volt and 5 volt high side driver outputs (VGATE5 and VGATE3). This signal may also be used as a switching signal for the 12 volt supply. FAULT# (4) An open-drain, active-low output. It will be driven low whenever an over-current condition is detected. It will be reset at the same time that the VGATE outputs are turned back on after a reset from the host on the PWR_EN signal. HEALTHY# (15) An open-drain, active-low output indicating card side power inputs are above their reset trip levels. LOCAL_PCI_RST# (9) An open-drain active-low output. It is used to reset the backend circuitry on the add-in card. It is active whenever the card-side monitor inputs are below their respective VTRIP levels. It may also be driven low by a low input on the PCI_RST# pin. LOCAL_PCI_RST (20) An open-drain (PFET) active-high output. It operates in parallel with LOCAL_PCI_RST#, providing an active high reset signal which is required by many 8051 style MCUs. It is active whenever the card-side monitor inputs are below their respective VTRIP levels. It may also be driven active by a low input on the PCI_RST# pin. SGNL_VLD# (16) An open-drain, active-low output that indicates card side power is valid and the internal card side PCI_RST# timer has timed out. VGATE3 (22) A slew rate limited high side driver output for the 3.3V external power FET gate. The output-voltage is generated by an on-board charge pump. VGATE5 (27) A slew rate limited high side driver output for the 5V external power FET gate. The output voltage is generated by an on-board charge pump. 1VREF (5) This output provides a 1V reference for pre-charging the bus signal pins. Implementing a simple unity-gain ampli- fier circuit will allow pre-charging a large number of pins. ABSOLUTE MAXIMUM RATINGS* RECOMMENDED OPERATING CONDITIONS * Temperature Under Bias ......................... –55°C to 125°C Storage Temperature .............................. –65°C to 150°C Lead Solder Temperature (10 secs) ..................... 300 °C Terminal Voltage with Respect to GND: CARD_3V_MON, CARD_5V_MON, HST_3V_MON, SGNL_VLD#, HEALTHY#, LOCAL_PCI_RET#, VCC ........................................ 7V VGATE3, VGATE5, DRVREN# .................. 16V RESET ............................................ VCC + 0.7V All Others ........................................ VCC + 0.7V Junction Temperature..........................................150°C ESD Rating per JEDEC……………………………..2000V Latch-Up testing per JEDEC………………......+/- 100mA Temperature Range (Industrial)...……....-40° C to +85°C (Commercial)...……....-5° C to +70°C Supply Voltage………………….....….………2.7V to 5.5V Package Thermal Resistance ( θ JA) 28 Lead SOIC/SSOP...…………………………80oC/W Moisture Classification Level 1 (MSL 1) per J-STD- 020 RELIABILITY CHARACTERISTICS Data Retention……………………………..…..100 Years Endurance……………………….……….100,000 Cycles Note * - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. |
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同様の説明 - SMH4042ASBKN |
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