CS51033

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CIRCUIT DESCRIPTION

THEORY OF OPERATION

Control Scheme

The CS51033 monitors the output voltage to determine

reference voltage of 1.25 V during the oscillator’s charge

cycle, the PFET is turned on and remains on for the duration

of the charge time. The PFET gets turned off and remains off

during the oscillator’s discharge cycle time with the

maximum duty cycle to 80%. It requires 7.0 mV typical, and

method of control does not require any loop stability

compensation.

Startup

The CS51033 has an externally programmable Soft Start

feature that allows the output voltage to come up slowly,

preventing voltage overshoot on the output.

combination described by:

ICS + IT *

IT

55

)

IT

5

The internal Holdoff Comparator ensures that the external

(F2) from being set. This allows the oscillator to reach its

operating frequency before enabling the drive output. Soft

reference input to approximately 1/2 of the voltage at the CS

pin during startup, permitting the control loop and the output

voltage to slowly increase. Once the CS pin charges above

the Holdoff Comparator trip point of 0.7 V, the low feedback

comparator reference to 1.25 V completing the startup cycle.

Lossless Short Circuit Protection

The CS51033 has “lossless” short circuit protection since

there is no current sense resistor required. When the voltage

at the CS pin (the fault timing capacitor voltage ) reaches

2.5 V, the fault timing circuitry is enabled. During normal

operation the CS voltage is 2.6 V. During a short circuit or

a transient condition, the output voltage moves lower and the

of the fault comparator goes high and the CS51033 goes into

a fast discharge mode. The fault timing capacitor, CS,

when the CS pin reaches 2.4 V, a valid fault condition has

been detected. The slow discharge comparator output goes

high and enables gate G5 which sets the slow discharge flip

turned off. The fault timing capacitor is slowly discharged

to 1.5 V. The CS51033 then enters a normal startup routine.

If the fault is still present when the fault timing capacitor

voltage reaches 2.5 V, the fast and slow discharge cycles

repeat as shown in Figure 3.

a fault condition is not detected, normal operation resumes

and CS charges back to 2.6 V. This reduces the chance of

erroneously detecting a load transient as a fault condition.

1.15 V

1.25 V

0 V

1.5 V

2.4 V

2.6 V

2.5 V

0 V

START

NORMAL OPERATION

FAULT

td1

S1

S2

S1

S2

S3

S3

S1

S2

S3

S3