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CS51033GDR8 データシート(PDF) 8 Page - ON Semiconductor

部品番号 CS51033GDR8
部品情報  Fast PFET Buck Controller
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CS51033GDR8 データシート(HTML) 8 Page - ON Semiconductor

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CS51033
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8
If we choose an arbitrary startup time of 200
µs, we
calculate the value of CS from:
T
+ CS
2.5 V
ICHARGE
CS(MIN) +
200
ms
264
mA
2.5 V
+ 0.02 mF
Use 0.1
µF.
The fault time out time is the sum of the slow discharge
time the fast discharge time and the recharge time and is
obviously dominated by the slow discharge time.
The first parameter is the slow discharge time, it is the time
for the CS capacitor to discharge from 2.4 V to 1.5 V and is
given by:
TSLOWDISCHARGE +
CS
(2.4 V
* 1.5 V)
IDISCHARGE
where IDISCHARGE is 6.0 µA typical.
TSLOWDISCHARGE + CS
1.5 V
105
The fast discharge time occurs when a fault is first
detected. The CS capacitor is discharged from 2.5 V to 2.4 V.
TFASTDISCHARGE +
CS
(2.5 V
* 2.4 V)
IFASTDISCHARGE
where IFASTDISCHARGE is 66 µA typical.
TFASTDISCHARGE + CS
1515
The recharge time is the time for CS to charge from 1.5 V
to 2.5 V.
TCHARGE +
CS
(2.5 V
* 1.5 V)
ICHARGE
where ICHARGE is 264 µA typical.
TCHARGE + CS
3787
The fault time out time is given by:
TFAULT + CS
(3787
) 1515 ) 1.5
105)
TFAULT + CS
(1.55
105)
For this circuit
TFAULT + 0.1
10*6
1.55
105
+ 0.0155
A larger value of CS will increase the fault time out time
but will also increase the Soft Start time.
8) Input Capacitor
The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage on
the VCC and VC pins. This capacitor must also ensure that
the VCC remains above the UVLO voltage in the event of an
output short circuit. CIN should be a low ESR capacitor of
at least 100
µF. A ceramic surface mount capacitor should
also be connected between VCC and ground to prevent
spikes.
9) MOSFET Selection
The CS51033 drives a P–channel MOSFET. The VGATE
pin swings from GND to VC. The type of PFET used
depends on the operating conditions but for input voltages
below 7.0 V a logic level FET should be used.
Choose a PFET with a continuous drain current (ID) rating
greater than the maximum output current. RDS(ON) should
be less than
RDS t+
0.6 V
IOUT(MAX)
167 m
W
The Gate–to–Source voltage VGS and the Drain–to
Source Breakdown Voltage should be chosen based on the
input supply voltage.
The power dissipation due to the conduction losses is
given by:
PD + IOUT2
RDS(ON)
D
The power dissipation due to the switching losses is given
by:
PD + 0.5
VIN
IOUT
(TRr ) TF)
FSW
where TR = Rise Time and TF = Fall Time.
10) Diode Selection
The flyback or catch diode should be a Schottky diode
because of it’s fast switching ability and low forward voltage
drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should be
at least 20 V for this 12 V application.
The diode power dissipation is given by:
PD + IOUT
VD
(1.0
* DMIN)


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