データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD1837AAS データシート(PDF) 11 Page - Analog Devices

部品番号 AD1837AAS
部品情報  2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
Download  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD1837AAS データシート(HTML) 11 Page - Analog Devices

Back Button AD1837AAS Datasheet HTML 7Page - Analog Devices AD1837AAS Datasheet HTML 8Page - Analog Devices AD1837AAS Datasheet HTML 9Page - Analog Devices AD1837AAS Datasheet HTML 10Page - Analog Devices AD1837AAS Datasheet HTML 11Page - Analog Devices AD1837AAS Datasheet HTML 12Page - Analog Devices AD1837AAS Datasheet HTML 13Page - Analog Devices AD1837AAS Datasheet HTML 14Page - Analog Devices AD1837AAS Datasheet HTML 15Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 24 page
background image
REV. A
AD1837A
–11–
FUNCTIONAL OVERVIEW
ADCs
There are two ADC channels in the AD1837A, configured as a
stereo pair. Each ADC has fully differential inputs. The ADC
section can operate at a sample rate of up to 96 kHz. The ADCs
include on-board digital decimation filters with 120 dB stop-band
attenuation and linear phase response, operating at an oversam-
pling ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz
operation).
ADC peak level information for each ADC may be read from the
ADC Peak 0 and ADC Peak 1 registers. The data is supplied as
a 6-bit word with a maximum range of 0 dB to –63 dB and a
resolution of 1 dB. The registers will hold peak information until
read; after reading, the registers are reset so that new peak
information can be acquired. Refer to the register description
for details on the format. The two ADC channels have a com-
mon serial bit clock and a left-right framing clock. The clock
signals are all synchronous with the sample rate.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the
M/S pin to
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1837A will generate the timing signals. When
the pins are set as inputs, the timing must be generated by
the external audio controller.
DACs
The AD1837A has eight DAC channels arranged as four inde-
pendent stereo pairs, with eight single-ended analog outputs for
improved noise and distortion performance. Each channel has
its own independently programmable attenuator, adjustable in
1024 linear steps. Digital inputs are supplied through four serial
data input pins (one for each stereo pair) and a common frame
(DLRCLK) and bit (DBLCK) clock. Alternatively, one of the
packed data modes may be used to access all eight channels on a
single TDM data pin. A stereo replicate feature is included where
the DAC data sent to the first DAC pair is also sent to the
other DACs in the part. The AD1837A can accept DAC data at
a sample rate of 192 kHz on DAC 1 only. The stereo repli-
cate feature can then be used to copy the audio data to the
other DACs.
Each of the output pins sits at a dc level of VREF and swings
±1.4 V for a 0 dB digital input signal. A single op amp third-
order external low-pass filter is recommended to remove high
frequency noise present on the output pins. Note that the use of
op amps with low slew rate or low bandwidth may cause high
frequency noise and tones to fold down into the audio band;
care should be exercised in selecting these components.
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases, this capacitor may be eliminated with little affect
on performance.
DAC and ADC Coding
The DAC and ADC output data stream is in a twos comple-
ment encoded format. The word width can be selected from
16 bit, 20 bit, or 24 bit. The coding scheme is detailed
in Table I.
Table I. Coding Scheme
Code
Level
0111 . . . . 11111
+FS
0000 . . . . 00000
0 (Ref Level)
1000 . . . . 00000
–FS
AD1837A CLOCKING SCHEME
By default, the AD1837A requires an MCLK signal that is
256 times the required sample frequency up to a maximum of
12.288 MHz. The AD1837A uses a clock scaler to double the
clock frequency for internal use. The default setting of the clock
scaler is multiply by two. The clock scaler can also be set to
multiply by 1 (bypass) or multiply by 2/3. The internal MCLK
signal, IMCLK, should not exceed 24.576 MHz in order to
ensure correct operation.
The MCLK of the AD1837A should remain constant during
normal operation of the DAC and ADC. If it is required to
change the MCLK rate, the AD1837A should be reset. Addition-
ally, if MCLK scaler needs to be modified so that the IMCLK
does not exceed 24.576 MHz, this should be done during the
internal reset phase of the AD1837A by programming the bits in
the first 3072 MCLK periods following the reset.
Selecting DAC Sampling Rate
The AD1837A DAC engine has a programmable interpolator
that allows the user to select different interpolation rates
based on the required sample rate and MCLK value avail-
able. Table II shows the settings required for sample rates
based on a fixed MCLK of 12.288 MHz.
Table II. DAC Sample Rate Settings
Sample Rate
Interpolator Rate
DAC Control 1 Register
48 kHz
8x
000000xxxxxxxx00
96 kHz
4x
000000xxxxxxxx01
192 kHz
2x
000000xxxxxxxx10
Selecting an ADC Sample Rate
The AD1837A ADC engine has a programmable decimator
that allows the user to select the sample rate based on the
MCLK value. By default, the output sample rate is IMCLK/
512. To achieve a sample rate of IMCLK/256, the sample
rate bit in the ADC Control 1 register should be set as shown
in Table III.
Table III. ADC Sample Rate Settings
Sample Rate
ADC Control 1 Register
IMCLK/512
1100000xx0xxxxxx (48 kHz)
IMCLK/256
1100000xx1xxxxxx (96 kHz)
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less
than 300 ps rms, measured using the edge-to-edge technique.
Even at these levels, extra noise or tones may appear in the


同様の部品番号 - AD1837AAS

メーカー部品番号データシート部品情報
logo
Analog Devices
AD1837AS AD-AD1837AS Datasheet
523Kb / 24P
   2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
REV. B
AD1837AS-REEL AD-AD1837AS-REEL Datasheet
523Kb / 24P
   2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
REV. B
AD1837A AD-AD1837A_15 Datasheet
407Kb / 24P
   2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
REV. A
More results

同様の説明 - AD1837AAS

メーカー部品番号データシート部品情報
logo
Analog Devices
AD1835 AD-AD1835_15 Datasheet
705Kb / 24P
   2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
REV. B
AD1837A AD-AD1837A_15 Datasheet
407Kb / 24P
   2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
REV. A
AD1837 AD-AD1837 Datasheet
523Kb / 24P
   2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
REV. B
AD1835 AD-AD1835 Datasheet
326Kb / 23P
   2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
REV. PrA
AD1837 AD-AD1837_15 Datasheet
533Kb / 24P
   2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
REV. B
AD1838 AD-AD1838 Datasheet
424Kb / 24P
   2 ADC, 6 DAC,96 kHz, 24-Bit Codec
REV. 0
AD1838A AD-AD1838A_15 Datasheet
537Kb / 24P
   2 ADC, 6 DAC, 96 kHz, 24-Bit Codec
REV. A
AD1839 AD-AD1839_15 Datasheet
325Kb / 24P
   2 ADC, 6 DAC, 96 kHz, 24-Bit Codec
REV. B
AD1838 AD-AD1838_15 Datasheet
501Kb / 24P
   2 ADC, 6 DAC, 96 kHz, 24-Bit Codec
REV. A
AD1835A AD-AD1835A_15 Datasheet
281Kb / 24P
   2 ADC, 8 DAC, 96 kHz, 24-Bit Codecs
REV. A
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com