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ISD14B00 データシート(PDF) 8 Page - Nuvoton Technology Corporation

部品番号 ISD14B00
部品情報  SINGLE-CHIP, MULTIPLE-MESSAGE VOICE RECORD/PLAYBACK DEVICE
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メーカー  NUVOTON [Nuvoton Technology Corporation]
ホームページ  http://www.nuvoton.com
Logo NUVOTON - Nuvoton Technology Corporation

ISD14B00 データシート(HTML) 8 Page - Nuvoton Technology Corporation

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ISD14B00
Publication Release Date: Jan 19, 2009
- 8 -
Revision 0.30
PIN NAME
PIN #
I / O
FUNCTION
R
¯¯/P ( When Direct Mode is active):
 When R
¯¯/P is set to Low, level-hold record operation is selected.
When R
¯¯/P is set to High, edge-trigger & toggle on-off playback operation is
selected.
XCLK
¯¯¯¯¯/FMC3
25
I
External Clock: In Address Mode, low active and level-hold input. As XCLK
¯¯¯¯¯
activated, Rosc pin accepts external clock input signal, provided resistor at
Rosc must be removed. Connecting this pin to High enables device running
on internal clock via Rosc resistor. If not used, XCLK
¯¯¯¯¯ must be at high level.
When Direct Mode is active, FMC3, together with FMC1 & FMC2, setup
various fixed-message configurations.
FT
¯¯
26
I
Feed-Through: Low active input, Level-hold, debounce & Internal pull-up
required.
When FT
¯¯ is selected, the MIC+ input is configured to a single-
ended input with 1Vp-p maximum input amplitude and feed-through to the
speaker outputs.
Addr/ Drct
¯¯¯¯
27
I
Level-hold input.
Addr: When set to High, the device operates under Address Mode.
Level-hold input.
Drct
¯¯¯¯: When set to Low, the device operates under Direct Mode.
The
device reconfigures its pin definitions to fit various fixed-message
configurations utilizing FMC1 , FMC2 & FMC3 pins as below table.
FMC3
FMC2
FMC1
# of fixed messages
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
VCCD
28
I
Digital Power Supply: Power supply for digital circuits.
Notes:
[1] : Address bits S0, S1, S2, S3, E0, E1, E2 & E3 are used to access the memory location.


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