データシートサーチシステム |
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LM3200TL データシート(PDF) 2 Page - National Semiconductor (TI) |
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LM3200TL データシート(HTML) 2 Page - National Semiconductor (TI) |
2 / 15 page Connection Diagrams 20126102 Top View 20126103 Bottom View 10–Bump Thin Micro SMD Package, Large Bump See NS Package Number TLP10NHA Order Information Order Number Package Marking (Note) Supplied As LM3200TL XYTT SCUB 250 Units, Tape and Reel LM3200TLX XYTT SCUB 3000 Units, Tape and Reel Note: The package marking “XY” designates the date code. “TT” is a NSC internal code for die traceability. Pin Description Pin # Name Description A1 V DD Analog Supply Input. A 0.1 µF ceramic capacitor is recommended to be placed as close to this pin as possible. (Figure 1) B1 V CON Voltage Control Analog input. V CON controls VOUT in PWM mode. Set: VOUT =3xVCON. Do not leave floating. C1 FB Feedback Analog Input. Connect to the output at the output filter capacitor. (Figure 1) D1 BYP Bypass. Use this digital input to command operation in Bypass mode. Set BYP low for normal operation. D2 EN Enable Input. Set this digital input high after Vin >2.7V for normal operation. For shutdown, set low. D3 PGND Power Ground C3 SW Switching Node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit specification of the LM3200. B3 PV IN Power Supply Voltage Input to the internal PFET switch and Bypass FET. (Figure 1) A3 BYPOUT Bypass FET Drain. Connect to the output capacitor. (Figure 1) Do not leave floating. A2 SGND Analog and Control Ground www.national.com 2 |
同様の部品番号 - LM3200TL |
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同様の説明 - LM3200TL |
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