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SN74AUP1G34DCKR-PDSO-G5 データシート(PDF) 2 Page - Texas Instruments

部品番号 SN74AUP1G34DCKR-PDSO-G5
部品情報  LOW-POWER SINLE BUFFER GATE
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

SN74AUP1G34DCKR-PDSO-G5 データシート(HTML) 2 Page - Texas Instruments

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SN74AUP1G34
LOW POWER SINGLE BUFFER GATE
SCES603B – AUGUST 2004 – REVISED JUNE 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
This single buffer gate performs the Boolean function Y = A in positive logic.
NanoStar
 and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING‡
NanoStar
 − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Tape and reel
SN74AUP1G34YEPR
_ _ _H9_
−40
°C to 85°C
NanoFree
 − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Tape and reel
SN74AUP1G34YZPR
_ _ _H9_
−40
°C to 85°C
SOT (SOT-23) − DBV
Tape and reel
SN74AUP1G34DBVR
H34_
SOT (SC-70) − DCK
Tape and reel
SN74AUP1G34DCKR
H9_
SOT (SOT-553) − DRL
Reel of 4000
SN74AUP1G34DRLR
H9_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb,
= Pb-free).
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
H
L
L
logic diagram (positive logic)
AY
24


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