データシートサーチシステム |
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SN74ALVC74 データシート(PDF) 4 Page - Texas Instruments |
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SN74ALVC74 データシート(HTML) 4 Page - Texas Instruments |
4 / 8 page SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX fclock Clock frequency MHz t Pulse duration PRE or CLR low ns tw Pulse duration CLK high or low ns t Setup time Data before CLK ↑ ns tsu Setup time PRE or CLR inactive ns th Hold time Data after CLK ↑ ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT (INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN MAX fmax MHz t d CLK QorQ ns tpd PRE or CLR Q or Q ns operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS VCC = 1.8V VCC = 2.5 V VCC = 3.3 V UNIT PARAMETER TEST CONDITIONS TYP TYP TYP UNIT Cpd Power dissipation capacitance per flip-flop CL = 0, f = 10 MHz pF |
同様の部品番号 - SN74ALVC74 |
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同様の説明 - SN74ALVC74 |
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