74LVC1G74DP datasheet(2/19 Pages) PHILIPS

部品番号	74LVC1G74DP

部品情報	Single D-type flip-flop with set and reset; positive edge trigger

Download	19 Pages

Scroll/Zoom	100%

メーカー	PHILIPS [NXP Semiconductors]

ホームページ	http://www.nxp.com

Logo

2 / 19 page

2005 Feb 01

2

Philips Semiconductors

Product speciﬁcation

Single D-type ﬂip-ﬂop with set and

reset; positive edge trigger

74LVC1G74

FEATURES

• Wide supply voltage range from 1.65 V to 5.5 V

• 5 V tolerant inputs for interfacing with 5 V logic

• High noise immunity

• Complies with JEDEC standard:

– JESD8-7 (1.65 V to 1.95 V)

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V).

•±24 mA output drive (VCC = 3.0 V)

• ESD protection:

– HBM EIA/JESD22-A114-B exceeds 2000 V

– MM EIA/JESD22-A115-A exceeds 200 V.

• CMOS low power consumption

• Latch-up performance exceeds 250 mA

• Direct interface with TTL levels

• Inputs accept voltages up to 5 V

• Multiple package options

• Specified from −40 °C to +85 °C and −40 °C to +125 °C.

DESCRIPTION

The 74LVC1G74 is a high-performance, low-voltage,

Si-gate CMOS device, superior to most advanced CMOS

compatible TTL families.

The 74LVC1G74 is a single positive edge triggered D-type

flip-flop with individual data (D) inputs, clock (CP) inputs,

set (SD) and (RD) inputs, and complementary Q and Q

outputs.

This device is fully specified for partial power down

applications using Ioff. The Ioff circuitry disables the output,

preventing damaging backflow current through the device

when it is powered down.

The set and reset are asynchronous active LOW inputs

and operate independently of the clock input. Information

on the data input is transferred to the Q output on the

LOW-to-HIGH transition of the clock pulse. The D inputs

must be stable one set-up time prior to the LOW-to-HIGH

clock transition, for predictable operation.

Schmitt-trigger action at all inputs makes the circuit highly

tolerant to slower input rise and fall times.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = number of inputs switching;

Σ(CL × VCC2 × fo) = sum of the outputs.

2. The condition is VI = GND to VCC.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

propagation delay

CP to Q, QCL = 50 pF; VCC = 3.3 V

3.5

ns

SD to Q, QCL = 50 pF; VCC = 3.3 V

3.0

ns

RD to Q, QCL = 50 pF; VCC = 3.3 V

3.0

ns

fmax

maximum clock frequency

CL = 50 pF; VCC = 3.3 V

280

MHz

CI

input capacitance

4.0

pF

CPD

power dissipation capacitance

VCC = 3.3 V; notes 1 and 2

15

pF

同様の部品番号 - 74LVC1G74DP

メーカー	部品番号	データシート	部品情報
NXP Semiconductors	74LVC1G74DP	103Kb / 19P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 11-4 June 2012
	74LVC1G74DP	549Kb / 21P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 08-3 December 2009
	74LVC1G74DP	549Kb / 21P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 08-3 December 2009
	74LVC1G74DP	202Kb / 25P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 9-5 August 2010
	74LVC1G74DP	166Kb / 25P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 10-2 December 2011

More results

同様の説明 - 74LVC1G74DP

メーカー	部品番号	データシート	部品情報
NXP Semiconductors	74LVC1G74DC.125	299Kb / 25P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 12-2 April 2013
	74LVC1G74	202Kb / 25P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 9-5 August 2010
	74LVC2G74	100Kb / 20P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 01-3 November 2005
Nexperia B.V. All right...	74LVC1G74-Q100	245Kb / 16P	Single D-type flip-flop with set and reset; positive edge trigger
NXP Semiconductors	74LVC1G74	103Kb / 19P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 11-4 June 2012
	74LVC2G74	104Kb / 19P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 03-9 August 2007
	74LVC1G74	549Kb / 21P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 08-3 December 2009
	74LVC1G74	549Kb / 21P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 08-3 December 2009
	74LVC2G74	123Kb / 21P	Single D-type flip-flop with set and reset; positive edge trigger Rev. 06-23 December 2009
Nexperia B.V. All right...	74LVC2G74-Q100	231Kb / 15P	Single D-type flip-flop with set and reset; positive edge trigger