TC9208M
Preliminary Data Sheet
Pin Listing (continued)
No.
Pin label
Type
Description
TxData2_2
GMII/MII transmit data - bit 2
V7
PriBndw0
I/Opu
Priority bandwidth configuration pins. These configuration pins allow
the bandwidth percentage assigned to a priority packet queue to be
modified to certain hardwired levels. PriBndw chooses between 4
hardwired spreading percentage schemes among the 4 priority
queues of each port.
PriBndw(0)is latched on reset
TxData2_1
GMII/MII transmit data - bit 1
PriClass[2] is latched on reset
W7
PriClass2_1
I/Opd
Priority class - most significant bit.
TxData2_0
GMII/MII transmit data - least significant bit
Y7
PriClass0_0
I/Opu
Priority class - least significant bit. Sets priority level per port basis.
PriClass[2] - '00' - port 2 low priority
PriClass[2] - '01' - port 2 has normal priority
PriClass[2] - '10' - port 2 has high priority
PriClass[2] - '11' - port 2 has very high priority
PriClass[2] is latched on reset
V9
TxEn2
O
GMII/MII transmit enable
W6
GTxClk2
O
GMII transmit clock
F17
Vss 2.0
G
Digital ground for core
Y10 TxEr2
I/Opd Transmit Error
Y6
TxClk2
I
MII transmit clock
W1
Crs2
Is
MII carrier sense indication
W3
Col2
Is
MII collision indication
Y5
RxEr2
Is
Receive Error
K17 Vdd 3.3
P
Digital +3.3V power supply for I/O
V6
RxClk2
I
MII receive clock
W5
RxDv2
Is
GMII/MII data valid
W2
RxData2_0
Is
GMII receive data - least significant nibble.
MII receive data
Y1
RxData2_1
Is
GMII receive data - least significant nibble.
MII receive data
Y2
RxData2_2
Is
GMII receive data - least significant nibble.
MII receive data
D16 Vss 3.3
G
Digital ground for I/O
Y3
RxData2_3
Is
GMII receive data - least significant nibble.
MII receive data
V4
RxData2_4
Is
GMII receive data - most significant nibble
W4
RxData2_5
Is
GMII receive data - most significant nibble
Y4
RxData2_6
Is
GMII receive data - most significant nibble
V5
RxData2_7
Is
GMII receive data - most significant nibble
Confidential.
11/53
August 1, 2003
Copyright © 2003, IC Plus Corp.
TC9208M-DS-R06