3965 DMOS Dual Full Bridge

PWM Motor Driver

5

Functional Description

device into a minimum current draw mode. All circuits are

disabled including the VDD undervoltage monitor.

outputs of the device are disabled until the fault condition is

UVLO circuit disables the drivers

fixed frequency PWM control circuit. When the outputs of

the DMOS H-bridge are turned on, current increases in the

motor winding until it reaches a value given by:

At the trip point, the sense comparator resets the source

enable latch, turning off the source. At this point, load

inductance causes the current to recirculate until the end

fixed frequency cycle. (see timing diagram)

compared to the voltage across the sense resistor to set the

value of bridge current that will trip the PWM comparator.

output.

sets the oscillator frequency as follows:

spike occurs due to the reverse recovery currents of the

clamp diodes and/or switching transients related to

distributed capacitance in the load. To prevent this current

spike from erroneously resetting the source enable latch, the

sense comparator is blanked. The blank duration is

determined by the time it takes to charge the external RC

DMOS outputs. VREG is internally monitored and in the

case of a fault condition, the outputs of the device are

disabled. The VREG pin should be decoupled with a 0.22

µF capacitor to ground.

supply above VBB to drive the source side DMOS gates. A

0.22 uF ceramic monolithic capacitor should be connected

ceramic monolithic capacitor should be connected between

in the case of a fault condition the outputs of the device are

disabled.

when the junction temperature reaches 165°C typically. It is

intended only to protect the device from failures due to

excessive junction temperatures and should not imply that

output short circuits are permitted. Thermal shutdown has a

hysteresis of approximately 15°C.