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HCPL-J314 データシート(PDF) 8 Page - Agilent(Hewlett-Packard) |
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HCPL-J314 データシート(HTML) 8 Page - Agilent(Hewlett-Packard) |
8 / 17 page 8 Switching Specifications (AC) Over recommended operating conditions unless otherwise specified. Test Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note Propagation Delay Time to tPLH 0.1 0.2 0.7 µs Rg = 47 Ω, 10,11, 14 High Output Level Cg = 3 nF, 12,13, Propagation Delay Time to tPHL 0.1 0.3 0.7 µs f = 10 kHz, 14,17 Low Output Level Duty Cycle = Propagation Delay PDD -0.5 0.5 µs 50%, 10 Difference Between Any IF = 8 mA, Two Parts or Channels VCC = 30 V Rise Time tR 50 ns Fall Time tF 50 ns Output High Level Common |CMH| 10 30 kV/ µsTA = 25°C, 18 11 Mode Transient Immunity VCM = 1.5 kV Output Low Level Common |CML| 10 30 kV/ µs18 12 Mode Transient Immunity Package Characteristics For each channel unless otherwise specified. Test Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note Input-Output Momentary VISO 3750 Vrms TA=25 °C, 8,9 Withstand Voltage RH<50% for Output-Output Momentary VO-O 1500 Vrms 1 min. 15 Withstand Voltage Input-Output Resistance RI-O 1012 Ω VI-O=500 V 9 Input-Output Capacitance CI-O 1.2 pF Freq=1 MHz Notes: 1. Derate linearly above 70 °C free air temperature at a rate of 0.3 mA/°C. 2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 0.4 A. See Application section for additional details on limiting IOL peak. 3. Derate linearly above 85 °C, free air temperature at the rate of 4.0 mW/°C. 4. Input power dissipation does not require derating. 5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%. 6. In this test, VOH is measured with a DC load current. When driving capacitive load VOH will approach VCC as IOH approaches zero amps. 7. Maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. In accordance with UL 1577, each HCPL-J314 optocoupler is proof tested by applying an insulation test voltage ≥ 5000 V rms for 1 second (leakage detection current limit II-O ≤ 5 µA). This test is performed before 100% production test for partial discharge (method B) shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable. 9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 10. PDD is the difference between tPHL and tPLH between any two parts or channels under the same test conditions. 11. Common mode transient immunity in the high state is the maximum tolerable |dVcm/dt| of the common mode pulse VCM to assure that the output will remain in the high state (i.e. Vo > 6.0 V). 12. Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e. Vo < 1.0 V). 13. This load condition approximates the gate load of a 1200 V/25 A IGBT. 14. For each channel. The power supply current increases when operating frequency and Qg of the driven IGBT increases. 15. Device considered a two terminal device: Channel one output side pins shorted together, and channel two output side pins shorted together. |
同様の部品番号 - HCPL-J314 |
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同様の説明 - HCPL-J314 |
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