データシートサーチシステム |
|
CDB4271 データシート(PDF) 4 Page - Cirrus Logic |
|
CDB4271 データシート(HTML) 4 Page - Cirrus Logic |
4 / 53 page CS4271 4 DS592F1 6.1 SPI Mode ......................................................................................................................... 35 6.2 I²C Mode .......................................................................................................................... 36 7. REGISTER QUICK REFERENCE .......................................................................................... 37 8. REGISTER DESCRIPTION .................................................................................................... 38 8.1 Mode Control 1 - Address 01h ......................................................................................... 38 8.1.1 Functional Mode (Bits 7:6) .................................................................................. 38 8.1.2 Ratio Select (Bits 5:4) ......................................................................................... 38 8.1.3 Master / Slave Mode (Bit 3) ................................................................................. 38 8.1.4 DAC Digital Interface Format (Bits 2:0) ............................................................... 38 8.2 DAC Control - Address 02h ............................................................................................. 39 8.2.1 Auto-Mute (Bit 7) ................................................................................................. 39 8.2.2 Interpolation Filter Select (Bit 6) .......................................................................... 39 8.2.3 De-Emphasis Control (Bits 5:4) ........................................................................... 39 8.2.4 Soft Volume Ramp-Up After Error (Bit 3) ............................................................ 40 8.2.5 Soft Ramp-Down Before Filter Mode Change (Bit 2) .......................................... 40 8.2.6 Invert Signal Polarity (Bits 1:0) ............................................................................ 40 8.3 DAC Volume & Mixing Control - Address 03h ................................................................. 40 8.3.1 Channel B Volume = Channel A Volume (Bit 6) ................................................. 40 8.3.2 Soft Ramp or Zero Cross Enable (Bits 5:4) ......................................................... 40 8.3.3 ATAPI Channel Mixing and Muting (Bits 3:0) ...................................................... 41 8.4 DAC Channel A Volume Control - Address 04h .............................................................. 42 8.5 DAC Channel B Volume Control - Address 05h .............................................................. 42 8.5.1 Mute (Bit 7) .......................................................................................................... 42 8.5.2 Volume Control (Bits 6:0) .................................................................................... 42 8.6 ADC Control - Address 06h ............................................................................................. 43 8.6.1 Dither for 16-Bit Data (Bit 5) ................................................................................ 43 8.6.2 ADC Digital Interface Format (Bit 4) .................................................................... 43 8.6.3 ADC Channel A & B Mute (Bits 3:2) .................................................................... 43 8.6.4 Channel A & B High Pass Filter Disable (Bits 1:0) .............................................. 43 8.7 Mode Control 2 - Address 07h ......................................................................................... 43 8.7.1 Digital Loopback (Bit 4) ....................................................................................... 43 8.7.2 AMUTEC = BMUTEC (Bit 3) ............................................................................... 43 8.7.3 Freeze (Bit 2) ...................................................................................................... 44 8.7.4 Control Port Enable (Bit 1) .................................................................................. 44 8.7.5 Power Down (Bit 0) ............................................................................................. 44 8.8 Chip ID - Register 08h .....................................................................................................44 8.8.1 Chip ID (Bits 7:4) ................................................................................................. 44 8.8.2 Chip Revision (Bits 3:0) ....................................................................................... 44 9. PARAMETER DEFINITIONS .................................................................................................. 45 10. PACKAGE DIMENSIONS ..................................................................................................... 46 11. APPENDIX ............................................................................................................................ 47 |
同様の部品番号 - CDB4271 |
|
同様の説明 - CDB4271 |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |