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RTL8101L データシート(PDF) 6 Page - List of Unclassifed Manufacturers

部品番号 RTL8101L
部品情報  REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC97 CONTROLLER WITH POWER MANAGEMENT
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メーカー  ETC1 [List of Unclassifed Manufacturers]
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RTL8101L
2003-05-28
Rev.1.3
6
4. Pin Description
Note that some pins have multiple functions. Refer to the Pin Assignment diagram for a graphical representation.
4.1 Power Management/Isolation Interface
Symbol
Type
Pin No
Description
PMEB
(PME#)
O/D
57
Power management event: Open drain, active low. Used by the
RTL8101L to request a change in its current power management state
and/or to indicate that a power management event has occurred.
ISOLATEB
(ISOLATE#)
I
74
Isolate pin: Active low. Used to isolate the RTL8101L from the PCI
bus. The RTL8101L does not drive its PCI outputs (excluding PME#)
and does not sample its PCI input (including RST# and PCICLK) as long
as the Isolate pin is asserted.
LWAKE
O
64
LAN WAKE-UP signal: This signal is used to inform the motherboard
to execute the wake-up process. The motherboard must support
Wake-On-LAN (WOL). There are 4 choices of output, including active
high, active low, positive pulse, and negative pulse, that may be asserted
from the LWAKE pin. Please refer to the LWACT bit in the CONFIG1
register and the LWPTN bit in the CONFIG4 register for the setting of
this output signal. The default output is an active high signal.
Once a PME event is received, the LWAKE and PMEB assert at the
same time when the LWPME (bit4, CONFIG4) is set to 0. If the
LWPME is set to 1, the LWAKE asserts only when the PMEB asserts
and the ISOLATEB is low.
This pin is a 3.3V signaling output pin.
4.2 PCI Interface
Symbol
Type
Pin No
Description
AD31-0
T/S
85-87, 89, 91-93, 96,
8-15, 28-30, 32-36,
39-43, 45-47
PCI address and data multiplexed pins. AD31-24 are shared with
BootROM data pins, while AD16-0 are shared with BootROM address
pins.
C/BE3-0
T/S
84, 17, 27, 38
PCI bus command and byte enables multiplexed pins.
CLK
I
97
Clock: This PCI Bus clock provides timing for all transactions and bus
phases, and is input to PCI devices. The rising edge defines the start of
each phase. The clock frequency ranges from 0 to 33MHz.
DEVSELB
S/T/S
21
Device select: As a bus master, the RTL8101L samples this signal to
insure that a PCI target recognizes the destination address for the data
transfer. As a target, the RTL8101L asserts this signal low when it
recognizes its target address after FRAMEB is asserted.
FRAMEB
S/T/S
18
Cycle frame: As a bus master, this pin indicates the beginning and
duration of an access. FRAMEB is asserted low to indicate the start of a
bus transaction. While FRAMEB is asserted, data transfer continues.
When FRAMEB is deasserted, the transaction is in the final data phase.
As a target, the device monitors this signal before decoding the address
to check if the current transaction is addressed to it.
GNTB
I
82
Grant: This signal is asserted low to indicate to the RTL8101L that the
central arbiter has granted ownership of the bus to the RTL8101L. This
input is used when the RTL8101L is acting as a bus master.
REQB
T/S
83
Request: The RTL8101L will assert this signal low to request the
ownership of the bus from the central arbiter.


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