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ADC08D1500CIYB データシート(PDF) 4 Page - National Semiconductor (TI) |
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ADC08D1500CIYB データシート(HTML) 4 Page - National Semiconductor (TI) |
4 / 33 page Pin Descriptions and Equivalent Circuits (Continued) Pin Functions Pin No. Symbol Equivalent Circuit Description 18 19 CLK+ CLK- LVDS Clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See Section 1.1.2 for a description of acquiring the input and Section 2.3 for an overview of the clock inputs. 11 10 . 22 23 V INI+ V INI− . V INQ+ V INQ− Analog signal inputs to the ADC. The differential full-scale input range is 650 mV P-P when the FSR pin is low, or 870 mV P-P when the FSR pin is high. 7V CMO Common Mode Voltage. The voltage output at this pin is required to be the common mode input voltage at V IN+ and V IN− when d.c. coupling is used. This pin should be grounded when a.c. coupling is used at the analog inputs. This pin is capable of sourcing or sinking 100µA. See Section 2.2. 31 V BG Bandgap output voltage capable of 100 µA source/sink. 126 CalRun Calibration Running indication. This pin is at a logic high when calibration is running. 32 R EXT External bias resistor connection. Nominal value is 3.3k-Ohms (±0.1%) to ground. See Section 1.1.1. 34 35 Tdiode_P Tdiode_N Temperature Diode Positive (Anode) and Negative (Cathode) for die temperature measurements. See Section 2.6.2. www.national.com 4 |
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同様の説明 - ADC08D1500CIYB |
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