MC100EPT23 datasheet(2/8 Pages) ONSEMI

部品番号	MC100EPT23

部品情報	Dual Differential LVPECL to LVTTL Translator

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MC100EPT23

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2

1

2

3

45

6

7

8

Q0

GND

VCC

Figure 1. 8−Lead Pinout and Logic Diagram

D0

Q1

D1

D0

LVPECL

LVTTL

(Top View)

Table 1. PIN DESCRIPTION

Function

Q0, Q1

LVTTL Outputs

D0**, D1**

Differential LVPECL Inputs

VCC

Positive Supply

GND

Ground

** Pins will default to VCC/2 when left open.

Table 2. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

50 k

W

Internal Input Pullup Resistor

50 k

W

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 1500 V

> 100 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

Transistor Count

91 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

VCC

Power Supply

GND = 0 V

3.8

V

VI

Input Voltage

GND = 0 V

VI VCC

3.8

V

Iout

Output Current

Continuous

Surge

50

100

mA

TA

Operating Temperature Range

−40 to +85

°C

Tstg

Storage Temperature Range

−65 to +150

°C

qJA

Thermal Resistance (Junction−to−Ambient)

0 lfpm

500 lfpm

SOIC−8

190

130

°C/W

qJC

Thermal Resistance (Junction−to−Case)

Standard Board

SOIC−8

41 to 44

°C/W

qJA

Thermal Resistance (Junction−to−Ambient)

0 lfpm

500 lfpm

TSSOP−8

185

140

°C/W

qJC

Thermal Resistance (Junction−to−Case)

Standard Board

TSSOP−8

41 to 44

°C/W

Tsol

Wave Solder

< 2 to 3 sec @ 248

°C

265

°C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

同様の部品番号 - MC100EPT23

メーカー	部品番号	データシート	部品情報
ON Semiconductor	MC100EPT23	85Kb / 8P	3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator December, 2006 ??Rev. 15
	MC100EPT23	209Kb / 8P	Clock Management Design Using Low Skew and Low Jitter Devices June, 2001 ??Rev. 0
	MC100EPT23D	85Kb / 8P	3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator December, 2006 ??Rev. 15
	MC100EPT23D	202Kb / 20P	Evaluation Board Manual for High Frequency SOIC 8 August, 2004 ??Rev. 1
	MC100EPT23DG	85Kb / 8P	3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator December, 2006 ??Rev. 15

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同様の説明 - MC100EPT23

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ON Semiconductor	MC100EPT22	65Kb / 4P	Dual LVTTL/LVCMOS to Differential LVPECL Translator Sep, 1999 ??Rev. 2.0
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