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CAT24FC17GWETE13REV-F データシート(PDF) 4 Page - Catalyst Semiconductor |
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CAT24FC17GWETE13REV-F データシート(HTML) 4 Page - Catalyst Semiconductor |
4 / 10 page CAT24FC17 4 Doc. No. 1077, Rev. F © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice FUNCTIONAL DESCRIPTION The CAT24FC17 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24FC17 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. START BIT SDA STOP BIT SCL Figure 3. Start/Stop Timing Figure 2. Write Cycle Timing tWR STOP CONDITION START CONDITION ADDRESS ACK 8TH BIT BYTE n SCL SDA tHIGH SCL SDA IN SDA OUT tLOW tF tLOW tR tBUF tSU:STO tSU:DAT tHD:DAT tHD:STA tSU:STA tAA tDH Figure 1. Bus Timing PIN DESCRIPTIONS SCL: Serial Clock The CAT24FC17 serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin. SDA: Serial Data/Address The CAT24FC17 bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. WP: Write Protect This input, when tied to GND, allows write operations to the entire memory. When this pin is tied to VCC, the upper half of the memory array is write protected. When left floating or tied to VSS, normal read/write operations are allowed. |
同様の部品番号 - CAT24FC17GWETE13REV-F |
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同様の説明 - CAT24FC17GWETE13REV-F |
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