MC100LVEL38 datasheet(3/5 Pages) ONSEMI

部品番号	MC100LVEL38

部品情報	첨2, 첨4/6 Clock Generation Chip

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MC100LVEL38 MC100EL38

4–3

MOTOROLA

ECLinPS and ECLinPS Lite

DL140 — Rev 3

MC100LVEL38

DC CHARACTERISTICS (VEE = –3.8V to –3.0; VCC = GND)

–40

°C

0

°C

25

°C

85

°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

IEE

Power Supply Current

50

60

50

60

50

60

54

65

mA

VBB

Output Reference Voltage

–1.38

–1.26

–1.38

–1.26

–1.38

–1.26

–1.38

–1.26

V

IIH

Input High Current

150

µΑ

MC100LVEL38

AC CHARACTERISTICS (VEE = –3.8V to –3.0; VCC = GND)

–40

°C

0

°C

25

°C

85

°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

fMAX

Maximum Toggle Frequency

1000

MHz

tPLH

tPHL

Propagation Delay

CLK

→ Q (Diff)

to Output

CLK

→ Q (S.E.)

CLK

→ Phase_Out (Diff)

CLK

→ Phase_Out (S.E.)

MR

→ Q

760

710

800

750

510

960

1010

1000

1050

810

780

730

820

770

530

980

1030

1020

1070

830

800

750

840

790

540

1000

1050

1040

1090

840

850

800

890

840

570

1050

1100

1090

1140

870

ps

tSKEW

Within-Device Skew1

Q0 – Q3

All

50

75

50

75

50

75

50

75

ps

Part-to-Part

Q0 – Q3 (Diff)

All

200

240

200

240

200

240

200

240

tS

Setup Time

EN

→ CLK

DIVSEL

→ CLK

150

ps

tH

Hold Time

CLK

→ EN

CLK

→ Div_Sel

150

200

150

200

150

200

150

200

ps

VPP2

Minimum Input Swing

CLK

250

mV

VCMR3

Common Mode Range

CLK

–0.55

See3

–0.55

See3

–0.55

See3

–0.55

See3

V

tRR

Reset Recovery Time

100

ps

tPW

Minimum Pulse Width

CLK

MR

800

700

800

700

800

700

800

700

ps

tr, tf

Output Rise/Fall Times Q (20% – 80%)

280

550

280

550

280

550

280

550

ps

1. Skew is measured between outputs under identical transitions.

2. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.

3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within

the specified range and the peak-to-peak voltage lies between VPP Min and 1.0V. The lower end of the CMR range is dependent on VEE and

is equal to VEE + 1.65V.

同様の部品番号 - MC100LVEL38

メーカー	部品番号	データシート	部品情報
ON Semiconductor	MC100LVEL38	123Kb / 7P	3.3V ECL 첨2, 첨4/6 Clock Generation Chip November, 2006 ??Rev. 8
	MC100LVEL38	242Kb / 7P	3.3V ECL Clock Generation Chip July, 2016 ??Rev. 11
	MC100LVEL38DW	123Kb / 7P	3.3V ECL 첨2, 첨4/6 Clock Generation Chip November, 2006 ??Rev. 8
	MC100LVEL38DWG	123Kb / 7P	3.3V ECL 첨2, 첨4/6 Clock Generation Chip November, 2006 ??Rev. 8
	MC100LVEL38DWG	242Kb / 7P	3.3V ECL Clock Generation Chip July, 2016 ??Rev. 11

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同様の説明 - MC100LVEL38

メーカー	部品番号	データシート	部品情報
Motorola, Inc	MC100LVEL39	127Kb / 4P	첨2/4,첨4/6 Clock Generation Chip
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ON Semiconductor	MC100EL38	122Kb / 7P	5V ECL 첨2, 첨4/6 Clock Generation Chip October, 2006 ??Rev. 7
Micrel Semiconductor	SY100S838	73Kb / 4P	(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP
ON Semiconductor	MC100LVEL38	123Kb / 7P	3.3V ECL 첨2, 첨4/6 Clock Generation Chip November, 2006 ??Rev. 8
Micrel Semiconductor	SY100S839V	68Kb / 5P	첨2/4, 첨4/5/6 CLOCK GENERATION CHIP
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