MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–1

REV 2

7/96

8Bit Ripple Counter

The MC10E/100E137 is a very high speed binary ripple counter. The

two least significant bits were designed with very fast edge rates while the

more significant bits maintain standard ECLinPS

™ output edge rates.

This allows the counter to operate at very high frequencies while

maintaining a moderate power dissipation level.

The device is ideally suited for multiple frequency clock generation as

well as a counter in a high performance ATE time measurement board.

Both asynchronous and synchronous enables are available to

maximize the device’s flexibility for various applications. The

asynchronous enable input, A_Start, when asserted enables the counter

while overriding any synchronous enable signals. The E137 features

XORed enable inputs, EN1 and EN2, which are synchronous to the CLK

input. When only one synchronous enable is asserted the counter

becomes disabled on the next CLK transition; all outputs remain in the

previous state poised for the other synchronous enable or A_Start to be

asserted to re-enable the counter. Asserting both synchronous enables

causes the counter to become enabled on the next transition of the CLK.

If EN1 (or EN2) and CLK edges are coincident, sufficient delay has been

inserted in the CLK path (to compensate for the XOR gate delay and the

internal D-flip flop setup time) to insure that the synchronous enable

signal is clocked correctly, hence, the counter is disabled.

The E137 can also be driven single-endedly utilizing the VBB output

supply as the voltage reference for the CLK input signal. If a single-ended

signal is to be used the VBB pin should be connected to the CLK input and

bypassed to ground via a 0.01

µF capacitor. VBB can only source/sink

0.5mA, therefore it should be used as a switching reference for the E137

only.

All input pins left open will be pulled LOW via an input pulldown resistor. Therefore, do not leave the differential CLK inputs

open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias

regulators and jeopardizing the stability of the device.

The asynchronous Master Reset resets the counter to an all zero state upon assertion.

CLK

CLK

LOGIC DIAGRAM

Q

Q

CLK

CLK

D

R

Q

Q

CLK

CLK

D

R

EN1

EN2

CLK

CLK

A_Start

Q

Q

D

R

Q0

Q0

Q1

Q1

Q

Q

CLK

CLK

D

R

Q7

Q7

MR

VBB

MC10E137

MC100E137

8-BIT RIPPLE

COUNTER

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

CLK, CLK

Q0-Q7, Q0-Q7

A_Start

EN1, EN2

MR

VBB

Differential Clock Inputs

Differential Q Outputs

Asynchronous Enable Input

Synchronous Enable Inputs

Asynchronous Master Reset

Switching Refernce Output

PIN

FUNCTION

PIN NAMES