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SmartASIC, Inc.
SD1010A
November, 1999
SmartASIC Confidential
11
Revision B
CPU_SDA
5
I/O
SDA in I
2C for CPU interface
PWM_CTL
6
O
PWM control signal (Detail description in PWM
Operation Section)
CLK_1M
7
I
Free Running Clock (default: 1MHz)
CLK_1M_O
9
O
Feedback of free Running Clock
RESET_B
10
I
System Reset ( active LOW)
HSYNC_X
31
O
Default HSYNC generated by ASIC (active LOW)
R_OSD
11
I
OSD Color Red
G_OSD
12
I
OSD Color Green
B_OSD
13
I
OSD Color Blue
EN_OSD
14
I
OSD Mixer Enable
=0, No OSD output
=1,R_OUT[7:0]= {R_OSD repeat 8 times}
G_OUT[7:0]= {G_OSD repeat 8 times }
B_OUT[7:0]= {B_OSD repeat 8 times }
SCAN_EN
15
I
Manufacturing test pin (NC)
TEST_EN
16
I
Manufacturing test pin (NC)
VDD
8
Power Supply
VDD
26
Power Supply
VDD
41
Power Supply
VDD
52
Power Supply
VDD
62
Power Supply
VDD
76
Power Supply
VDD
77
Power Supply
VDD
84
Power Supply
VDD
94
Power Supply
VDD
100
Power Supply
VDD
106
Power Supply
VDD
113
Power Supply
VDD
118
Power Supply
VDD
128
Power Supply
GND
3
Ground
GND
25
Ground
GND
36
Ground
GND
46
Ground
GND
56
Ground
GND
57
Ground
GND
67
Ground
GND
68
Ground
GND
79
Ground
GND
89
Ground
GND
99
Ground
GND
101
Ground
GND
112
Ground
GND
114
Ground
GND
124
Ground
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