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データシートサーチシステム |
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データシートサーチシステム |
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CAT24FC32ALTE13 データシート(PDF) 10 Page - Catalyst Semiconductor |
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CAT24FC32ALTE13 データシート(HTML) 10 Page - Catalyst Semiconductor |
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10 / 12 page  CAT24FC32A 10 Doc. No. 1048, Rev. F to address N, the READ immediately following would access data from address N+1. If N=E (where E=4095), then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT24FC32A receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After CAT24FC32A acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT24FC32A then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24FC32A sends the initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24FC32A will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation will terminate when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from CAT24FC32A is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24FC32A address bits so that the entire memory array can be read during one operation. After the last memory address is read out, the counter will ‘wrap around’ and continue to clock out data bytes. Figure 12. Selective Read Timing X = Don't care bit Figure 13. Sequential Read Timing BUS ACTIVITY: MASTER SDA LINE DATA n+x DATA n A C K A C K DATA n+1 A C K S T O P N O A C K DATA n+2 A C K P SLAVE ADDRESS XX A15—A8 SLAVE ADDRESS S A C K A C K A C K BUS ACTIVITY: MASTER SDA LINE S T A R T A7—A0 BYTE ADDRESS SLAVE ADDRESS S A C K N O A C K S T A R T DATA P S T O P XX |
同様の部品番号 - CAT24FC32ALTE13 |
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同様の説明 - CAT24FC32ALTE13 |
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