TLF12640

ADVANCE INFORMATION

November 1996

74LCX273

Low-Voltage Octal D Flip-Flop

with 5V Tolerant Inputs and Outputs

General Description

The LCX273 has eight edge-triggered D-type flip-flops with

individual D inputs and Q outputs The common buffered

Clock (CP) and Master Reset (MR) input load and reset

(clear) all flip-flops simultaneously

The register is fully edge-triggered The state of each D in-

put one setup time before the LOW-to-HIGH clock tran-

sition is transferred to the corresponding flip-flop’s Q out-

put

All outputs will be forced LOW independently of Clock or

Data inputs by a LOW voltage level on the MR input The

device is useful for applications where the true output only is

required and the Clock and Master Reset are common to all

storage elements

tions with capability of interfacing to a 5V signal environ-

ment The LCX273 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing CMOS low power dissipation

Features

Y

5V tolerant inputs and outputs

Y

Y

Power-down high impedance inputs and outputs

Y

Supports live insertionwithdrawal

Y

Y

g

24 mA output drive

Y

reduction circuitry

Y

Functionally compatible with the 74 series 273

Y

Latch-up performance exceeds 500 mA

Y

ESD performance

Logic Symbols

TLF12640 – 1

IEEEIEC

TLF12640 – 2

Connection Diagram

Pin Assignment for

SOIC SSOP and TSSOP

TLF12640 – 3

Pin Names

Description

Data Inputs

MR

Master Reset

CP

Clock Pulse Input

Data Outputs

SOIC JEDEC

SOIC EIAJ

SSOP Type II

TSSOP JEDEC

Order Number

74LCX273WM

74LCX273SJ

74LCX273MSA

74LCX273MTC

74LCX273WMX

74LCX273SJX

74LCX273MSAX

74LCX273MTCX

See NS Package Number

M20B

M20D

MSA20

MTC20

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1996 National Semiconductor Corporation

RRD-B30M17Printed in U S A

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