データシートサーチシステム
Selected language   Japanese  ▼

Delete All
ON OFF
ALLDATASHEET.JP

X  

Preview PDF Download HTML

CDCDB2000 データシート(PDF) 20 Page - Texas Instruments

Click here to check the latest version.
部品番号. CDCDB2000
部品情報  CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
ダウンロード  33 Pages
Scroll/Zoom Zoom In 100% Zoom Out
メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo 

CDCDB2000 Datasheet(HTML) 20 Page - Texas Instruments

Zoom Inzoom in Zoom Outzoom out
 20 / 33 page
background image
20
CDCDB2000
SNAS787 – NOVEMBER 2019
www.ti.com
Product Folder Links: CDCDB2000
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
7.6.1.3 OECR3 Register (Address = 2h) [reset = FFh]
OECR3 is shown in Table 7.
Return to the Summary Table.
The OECR3 register contains bits that enable or disable individual output clock channels [15:8]
Table 7. OECR3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Output Enable, CK15
R/W
1h
This bit controls the output enable signal for output channel
CK15_P/CK15_N.
0h = Output Disabled
1h = Output Enabled
6
Output Enable, CK14
R/W
1h
This bit controls the output enable signal for output channel
CK14_P/CK14_N.
0h = Output Disabled
1h = Output Enabled
5
Output Enable, CK13
R/W
1h
This bit controls the output enable signal for output channel
CK13_P/CK13_N.
0h = Output Disabled
1h = Output Enabled
4
Output Enable, CK12
R/W
1h
This bit controls the output enable signal for output channel
CK12_P/CK12_N.
0h = Output Disabled
1h = Output Enabled
3
Output Enable, CK11
R/W
1h
This bit controls the output enable signal for output channel
CK11_P/CK11_N.
0h = Output Disabled
1h = Output Enabled
2
Output Enable, CK10
R/W
1h
This bit controls the output enable signal for output channel
CK10_P/CK10_N.
0h = Output Disabled
1h = Output Enabled
1
Output Enable, CK9
R/W
1h
This bit controls the output enable signal for output channel
CK9_P/CK9_N.
0h = Output Disabled
1h = Output Enabled
0
Output Enable, CK8
R/W
1h
This bit controls the output enable signal for output channel
CK8_P/CK8_N.
0h = Output Disabled
1h = Output Enabled
7.6.1.4 OERDBK Register (Address = 3h) [reset = 0h]
OERDBK is shown in Table 8.
Return to the Summary Table.
The OERDBK register contains bits that report the current state of the OE[12:5]# input pins.
Table 8. OERDBK Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OE12# State
R
0h
This bit reports the logic level present on the OE12# pin.
6
OE11# State
R
0h
This bit reports the logic level present on the OE11# pin.
5
OE10# State
R
0h
This bit reports the logic level present on the OE10# pin.
4
OE9# State
R
0h
This bit reports the logic level present on the OE9# pin.
3
OE8# State
R
0h
This bit reports the logic level present on the OE8# pin.


Html ページ

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33 


Datasheet Download




リンク URL



Privacy Policy
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   ブックマーク
   |   リンク交換   |   メーカーリスト
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn