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MC10EP56DT データシート(PDF) 7 Page - ON Semiconductor |
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MC10EP56DT データシート(HTML) 7 Page - ON Semiconductor |
7 / 8 page MC10EP56, MC100EP56 http://onsemi.com 7 Figure 2. Fmax/Jitter @ 255C FREQUENCY (GHz) 1 2 3 4 5 6 7 8 (JITTER) 9 3.3 V 10 800 1000 600 400 200 1.0 1.5 2.0 2.5 3.0 0 5 V V TT = V CC − 2.0 V W Driver Device Receiver Device QD 50 W 50 V TT Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 − Termination of ECL Logic Devices.) Q D Resource Reference of Application Notes AN1404 − ECLinPS Circuit Performance at Non−Standard VIH Levels AN1405 − ECL Clock Distribution Techniques AN1406 − Designing with PECL (ECL at +5.0 V) AN1504 − Metastability and the ECLinPS Family AN1568 − Interfacing Between LVDS and ECL AN1650 − Using Wire−OR Ties in ECLinPS Designs AN1672 − The ECL Translator Guide AND8001 − Odd Number Counters Design AND8002 − Marking and Date Codes AND8009 − ECLinPS Plus Spice I/O Model Kit AND8020 − Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. |
同様の部品番号 - MC10EP56DT |
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同様の説明 - MC10EP56DT |
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