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SN74SSTV32852 データシート(PDF) 1 Page - Texas Instruments |
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SN74SSTV32852 データシート(HTML) 1 Page - Texas Instruments |
1 / 10 page SN74SSTV32852 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Member of the Texas Instruments Widebus Family D 1-to-2 Outputs Support Stacked DDR DIMMs D Supports SSTL_2 Data Inputs D Outputs Meet SSTL_2 Class II Specifications D Differential Clock (CLK and CLK) Inputs D Supports LVCMOS Switching Levels on the RESET Input D RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low D Pinout Optimizes DIMM PCB Layout D One Device Per DIMM Required D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) description/ordering information This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible. The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING 0 °C to 70°C LFBGA – GKF Tape and reel SN74SSTV32852GKFR SV852 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2003, Texas Instruments Incorporated Widebus is a trademark of Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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同様の説明 - SN74SSTV32852 |
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