SN74SSTV32852

24-BIT TO 48-BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND OUTPUTS

SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003

5

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 1)

VCC = 2.5 V

± 0.2 V

UNIT

MIN

MAX

fclock

Clock frequency

200

MHz

tw

Pulse duration, CLK, CLK high or low

2.5

ns

tact

Differential inputs active time (see Note 5)

22

ns

tinact

Differential inputs inactive time (see Note 6)

22

ns

t

Setup time

Fast slew rate (see Notes 7 and 9)

Dt bf

CLK

↑ CLK↓

0.75

ns

tsu

Setup time

Slow slew rate (see Notes 8 and 9)

Data before CLK

↑, CLK↓

0.9

ns

th

Hold time

Fast slew rate (see Notes 7 and 9)

Data after CLK

↑ CLK↓

0.75

ns

th

Hold time

Slow slew rate (see Notes 8 and 9)

Data after CLK

↑, CLK↓

0.9

ns

NOTES:

5. VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high.

6. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken

low.

7. Data signal input slew rate

≥1 V/ns

8. Data signal input slew rate

≥0.5 V/ns and <1 V/ns

9. CLK, CLK input slew rates are

≥1 V/ns.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 2.5 V

± 0.2 V

UNIT

(INPUT)

(OUTPUT)

MIN

MAX

fmax

200

MHz

tpd

CLK and CLK

Q

1.1

3.1

ns

tPHL

RESET

Q

5

ns