MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–89

REV 6

9/96

Dual J-K Master-Slave

Flip-Flop

The MC10H135 is a dual J–K master–slave flip–flop. The device is provided

with an asynchronous set(s) and reset(R). These set and reset inputs overide

the clock.

A common clock is provided with separate J–K inputs. When the clock is

static, the JK inputs do not effect the output. The output states of the flip flop

change on the positive transition of the clock.

• Propagation delay, 1.5 ns Typical

• Improved Noise Margin 150

• Power Dissipation, 280 mW

mV (Over Operating Voltage

Typical/Pkg. (No Load)

and Temperature Range)

• ftog 250 MHz Max•

Voltage Compensated

• MECL 10K–Compatible

MAXIMUM RATINGS

Characteristic

Symbol

Rating

Unit

Power Supply (VCC = 0)

VEE

–8.0 to 0

Vdc

Input Voltage (VCC = 0)

VI

0 to VEE

Vdc

Output Current — Continuous

— Surge

Iout

50

100

mA

Operating Temperature Range

TA

0 to +75

°C

Storage Temperature Range — Plastic

— Ceramic

Tstg

–55 to +150

–55 to +165

°C

°C

ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)

0

°

25

°

75

°

Characteristic

Symbol

Min

Max

Min

Max

Min

Max

Unit

Power Supply Current

IE

—

75

—

68

—

75

mA

Input Current High

Pins 6, 7, 10, 11

Pins 4, 5, 12, 13

Pin 9

IinH

—

—

—

460

800

675

—

—

—

285

500

420

—

—

—

285

500

420

µA

Input Current Low

IinL

0.5

—

0.5

—

0.3

—

µA

High Output Voltage

VOH

–1.02

–0.84

–0.98

–0.81

–0.92

–0.735

Vdc

Low Output Voltage

VOL

–1.95

–1.63

–1.95

–1.63

–1.95

–1.60

Vdc

High Input Voltage

VIH

–1.17

–0.84

–1.13

–0.81

–1.07

–0.735

Vdc

Low Input Voltage

VIL

–1.95

–1.48

–1.95

–1.48

–1.95

–1.45

Vdc

AC PARAMETERS

Propagation Delay

Set, Reset, Clock

tpd

0.7

2.6

0.7

2.6

0.7

2.6

ns

Rise Time

tr

0.7

2.2

0.7

2.2

0.7

2.2

ns

Fall Time

tf

0.7

2.2

0.7

2.2

0.7

2.2

ns

Set–up Time

tset

1.5

—

1.5

—

1.5

—

ns

Hold Time

thold

1.0

—

1.0

—

1.0

—

ns

Toggle Frequency

ftog

250

—

250

—

250

—

MHz

NOTE:

Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,

after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit

board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a

50–ohm resistor to –2.0 volts.

LOGIC DIAGRAM

DIP PIN ASSIGNMENT

VCC1

Q1

Q1

R1

S1

K1

J1

VEE

VCC2

Q2

Q2

R2

S2

K2

J2

C

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

MC10H135

VCC1 = PIN 1

VCC2 = PIN 16

VEE = PIN 8

S1 5

J1 7

K1 6

R1 4

C 9

S2 12

J2 10

K2 11

R2 13

Q1

Q1

Q2

Q2

2

3

15

14

N.D. = Not Defined

RS TRUTH TABLE

RS

Qn + 1

L

L

L

H

L

H

Qn

H

L

N.D.

H

H

*Output states change on

positive transition of clock

for J–K input condition

present.

CLOCK J–K TRUTH TABLE*

J

K

Qn + 1

L

H

L

L

H

H

Qn

L

H

Qn

L

H

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

FN SUFFIX

PLCC

CASE 775–02

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion

Tables on page 6–11 of the Motorola MECL Data

Book (DL122/D).