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データシートサーチシステム |
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データシートサーチシステム |
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SLC90E66-UF データシート(PDF) 8 Page - SMSC Corporation |
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SLC90E66-UF データシート(HTML) 8 Page - SMSC Corporation |
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8 / 257 page  SMSC DS – SLC90E66 Page 8 Rev. 07/10/2002 7.3.1 PMSTS - Power Management Status Register (I/O) ..........................................................................136 7.3.2 PMEN - Power Management Resume Enable Register (I/O).............................................................137 7.3.3 PMCNTRL - Power Management Control Register (I/O)...................................................................137 7.3.4 PMTMR - Power Management Timer Register (I/O) ..........................................................................138 7.3.5 GPSTS - General Purpose Status Register (I/O) ..............................................................................139 7.3.6 GPEN - General Purpose Enable Register (I/O) ................................................................................140 7.3.7 PCNTRL - Processor Control Register (I/O)......................................................................................140 7.3.8 PLVL2 - Processor Level 2 Register (I/O) .........................................................................................141 7.3.9 PLVL3 - Processor Level 3 Register (I/O) .........................................................................................142 7.3.10 GLBSTS - Global Status Register (I/O) ..............................................................................................142 7.3.11 DEVSTS - Device Status Register (I/O) .............................................................................................143 7.3.12 GLBEN - Global Enable Register (I/O) ...............................................................................................144 7.3.13 GLBCTL - Global Control Register (I/O).............................................................................................145 7.3.14 DEVCTL - Device Control Register (I/O) ...........................................................................................146 7.3.15 GPIREG - General Purpose Input Register (I/O)................................................................................148 7.3.16 GPOREG - General Purpose Output Register (I/O) ...........................................................................148 7.4 SMBUS I/O REGISTERS.................................................................................................................................149 7.4.1 SMBHSTSTS - SMBus Host Status Register (I/O).............................................................................149 7.4.2 SMBSLVSTS - SMBus Slave Status Register (I/O)............................................................................150 7.4.3 SMBHSTCNT - SMBus Host Control Register (I/O) ..........................................................................151 7.4.4 SMBHSTCMD - SMBus Host Command Register (I/O) ....................................................................151 7.4.5 SMBHSTADD - SMBus Host Address Register (I/O) .........................................................................152 7.4.6 SMBHSTDAT0 - SMBus Host Data 0 Register (I/O) .........................................................................152 7.4.7 SMBHSTDAT1 - SMBus Host Data 1 Register (I/O) .........................................................................152 7.4.8 SMBBLKDAT - SMBus Block Data Register (I/O) .............................................................................153 7.4.9 SMBSLVCNT - SMBus Slave Control Register (I/O).........................................................................153 7.4.10 SMBSHDWCMD - SMBus Shadow Command Register (I/O)...........................................................154 7.4.11 SMBSLVEVT - SMBus Slave Event Register (I/O).............................................................................154 7.4.12 SMBSLVEVT - SMBus Slave Data Register (I/O) .............................................................................154 8.0 PCI/ISA BRIDGE FUNCTIONAL OVERVIEW...............................................................................................155 8.1 MEMORY AND IO ADDRESS MAP.....................................................................................................................155 8.1.1 I/O Accesses ......................................................................................................................................155 8.1.2 Memory Access..................................................................................................................................155 8.1.3 BIOS Memory Space..........................................................................................................................155 8.2 PCI INTERFACE ............................................................................................................................................157 8.2.1 PCI Transaction Termination..............................................................................................................157 8.2.2 PCI Bus Arbitration.............................................................................................................................158 8.2.3 PCI Parity ...........................................................................................................................................158 8.3 ISA/EIO INTERFACE .....................................................................................................................................158 8.4 DMA CONTROLLER.......................................................................................................................................158 8.4.1 DMA Transfer Modes .........................................................................................................................159 8.4.2 DMA Transfer Types ..........................................................................................................................159 8.4.3 DMA Timing .......................................................................................................................................160 8.4.4 DMA Buffer.........................................................................................................................................160 8.4.5 DREQ and nDACK Latency Control ...................................................................................................160 8.4.6 DMA Channel Priority.........................................................................................................................160 8.4.7 Address Compatibility Mode...............................................................................................................161 8.4.8 DMA Transfer Sizes ...........................................................................................................................161 8.4.9 Address Shifting in 16-Bit DMA I/O Transfer ......................................................................................161 8.4.10 Auto initialization ................................................................................................................................161 8.4.11 Special DMA Software Commands ....................................................................................................161 8.4.12 ISA Refresh........................................................................................................................................162 8.5 PCI DMA ....................................................................................................................................................162 8.5.1 PC/PCI DMA ......................................................................................................................................162 8.5.2 Distributed DMA (DDMA) ..................................................................................................................165 8.6 INTERRUPT CONTROLLER...............................................................................................................................167 8.6.1 Programming the Interrupt Controller .................................................................................................167 8.6.2 End of Interrupt Operation..................................................................................................................168 8.6.3 Modes of Operation............................................................................................................................169 8.6.4 Cascade Mode ...................................................................................................................................170 8.6.5 Edge and Level Triggered Mode ........................................................................................................170 8.6.6 Interrupt Masks...................................................................................................................................170 8.6.7 Interrupt Controller Status ..................................................................................................................171 8.6.8 Interrupt Steering................................................................................................................................171 |
同様の部品番号 - SLC90E66-UF |
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同様の説明 - SLC90E66-UF |
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