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CS3301-ISZ データシート(PDF) 8 Page - Cirrus Logic

部品番号 CS3301-ISZ
部品情報  Low-noise, Programmable Gain, Differential Amplifier
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メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

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CS3301
8
DS595F2
DIGITAL CHARACTERISTICS
Notes: 17. Device is intended to be driven with CMOS logic levels.
18. When CLK is tied to DGND, an internal oscillator provides a master clock at approximately 2 MHz. CLK
should be driven for synchronous system operation.
Parameter
Symbol
CS3301
Unit
Min
Typ
Max
Digital Characteristics
High Level Input Drive Voltage
(Note 17)VIH
0.6*VD
-
VD
V
Low Level Input Drive Voltage
(Note 17)VIL
0.0
-
0.8
V
Input Leakage Current
IIN
-+1+10
µA
Digital Input Capacitance
CIN
-9
-
pF
Rise Times, Digital Inputs Except CLK
tRISE
--
100
ns
Fall Times, Digital Inputs Except CLK
tFALL
--
100
ns
Master Clock Specifications
Master Clock Frequency
(Note 18)fCLK
2.0
2.048
2.2
MHz
Master Clock Duty Cycle
fDTY
40
-
60
%
Master Clock Rise Time
tRISE
-
-
25
ns
Master Clock Fall Time
tFALL
-
-
25
ns
Master Clock Jitter (In-Band or Aliased In-Band)
JTRIB
--
300
ps
Master Clock Jitter (Out-of-Band)
JTROB
--
1
ns
0.9 * V D
0.1 * V D
t fa ll
t rise
Figure 2. Digital Input Rise and Fall Times
Gain Selection
GAIN2
GAIN1
GAIN0
x1
0
0
0
x2
0
0
1
x4
0
1
0
x8
0
1
1
x16
1
0
0
x32
1
0
1
x64
1
1
0
reserved
1
1
1
Input Selection
MUX1
MUX0
800
Ω termination
0
0
INA only
1
0
INB only
0
1
INA + INB
1
1
Table 1. Digital Selections for Gain and Input Mux Control


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