CS4373

DS577F1

7

SWITCHING CHARACTERISTICS

Notes: 14. If MCLK is removed, the CS4373 enters a sleep mode state.

15. SYNC latched on MCLK falling edge, data output on next MCLK rising edge.

Parameter

Symbol

Min

Typ

Max

Unit

MCLK Frequency

Normal Power Mode

(Note 14)

Low Power Mode

-

-

2.048

1.024

-

-

MHz

MHz

MCLK Duty Cycle

40

-

60

%

MCLK Jitter (In-band or aliased in-band)

--

300

ps

MCLK Jitter (Out-of-band)

--

1

ns

Rise Times:

Any Digital Input

-

-

50

ns

Fall Times:

Any Digital Input

-

-

50

ns

SYNC Setup Time to MCLK falling

20

-

-

ns

SYNC Hold Time after MCLK falling

20

-

-

ns

MCLK

MSYNC

t

TDATA

0

(2.048 MHz)

(256 kHz)

t

mss

t

mclk

t

msync

t

tdat

t

msh

Figure 2. Timing

0.9*VD

0.1*VD

Figure 1. Rise and Fall Times