MC14512B

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6

LOGIC DIAGRAM

13

12

11

1

2

3

4

5

6

7

9

X7

X6

X5

X4

X3

X2

X1

X0

B

C

A

15

10

14

DISABLE

INHIBIT

Z

1

1

IN

OUT

IN

2

OUT

2

TRANSMISSION

GATE

SELECTED

DEVICE

MC14512B

MC14512B

MC14512B

LOAD

DATA

BUS

3–STATE MODE OF OPERATION

Output terminals of several MC14512B 8–Bit Data

Selectors can be connected to a single date bus as shown.

One MC14512B is selected by the 3–state control, and the

remaining devices are disabled into a high–impedance “off”

state. The number of 8–bit data selectors, N, that may be

connected to a bus line is determined from the output drive

(including fanout to other device inputs), and can be

calculated by:

N =

+ 1

N must be calculated for both high and low logic state of the

bus line.