データシートサーチシステム |
|
ISL6111CRZA データシート(PDF) 9 Page - Intersil Corporation |
|
ISL6111CRZA データシート(HTML) 9 Page - Intersil Corporation |
9 / 16 page 9 The average current on the -12V supply should not exceed 0.8A. Since the thermal restrictions on the +12V supply are more severe, the +12V supply restricts the use of the ISL6111 to applications where the ±12V supplies draw relatively little current. Since both supplies only have one degree of freedom, the value of ROCSET, the flexibility of programming is quite limited. For applications where more power is required on the +12V supply, contact your local Intersil sales representative for information on other Hot Plug solutions. B. Do not try to sense voltages across the external sense resistors that are less than 20mV as spurious faults due to noise and comparator input sensitivity may result. The minimum recommended RCRSET value is 3.0kΩ. This will set the nominal OC voltage thresholds at 39mV and 26mV for the 3.3V and 5V comparators respectively. C. Minimize VRSENSE so as to not significantly reduce the voltage delivered to the adapter card. Remember PCB trace and connector distribution voltage losses also need to be considered. Make sure that the RSENSE resistor can adequately handle the dissipated power. For best results use a 1% precision resistor with a low temperature coefficient. D. Minimize external FET rDS(ON). Low rDS(ON) or multiple MOSFETs in parallel are recommended. Current Regulation Delay Time to Latch-Off The CR time delay to latch-off, allows for a predetermined delay from the start of CR, to the simultaneous latch-off of all four supply switches to the load. This delay period is set by the capacitor value to ground from the CRTIM pin. This feature allows the ISL6111 to provide a current regulated soft start into all loads, and to delay immediate latch-off of the bus supply switches thus ignoring transient OC conditions. See Table 2. for CR duration vs CRTIM capacitance value. Caution: An additional concern about long CR durations along with MB supply droop is power-FET survivability. The primary purpose of a protection device such as the ISL6111 is to quickly isolate a faulted card from the voltage bus. Delaying the time to latch-off works against this primary concern so understand the limitations and realities. Since we use the same CRTIM cap timing cap for all supplies, we have to set that cap to a size large enough to allow the -12V to start up under the worst load for a given system. If we set this to a 75ms duration, then this 75ms time-out duration will also be used when one of the higher power supplies goes into current limiting after startup is complete. The highest power supplies, the 3.3V and 5V each run to a maximum of 25W, as allowed by the PCI spec. If our overcurrent duration is set to 75ms, then theoretically (but extremely unlikely) more than 25W can be dissipated in the external FET for that whole duration. The ISL6111 has a way over-current "WOC" circuit that faults the chip off instantly if this theoretical dead short happens so quickly that the current limiting circuitry can't keep up. In reality, overcurrent is more likely to not be a zero-ohm short, and only a fraction of the power is dissipated in the FET. Ensure adequate sizing of external FETs to carry additional current during CR period in linear operation. By looking at the SOA of the Siliconix Si4404DY FET and even presupposing the full 25W for 100ms duration for a single pulse is not an issue with this power FET. This FET is representative of FETs for a PCI application. If for a higher power non PCI design, consult the MOSFET vendor SOA curves. Application Considerations Soft Start and Turn-Off Considerations The ISL6111 does allow the user to select the rate of ramp up on the voltage supplies. This start-up ramp minimizes in- rush current at start-up while the on card bulk capacitors charge. The ramp is created by placing capacitors on M12VG, 3VG and 5VG to ground. These capacitors are each charged up by a nominal 25 µA current during turn on. The +12VO has internal current controlled ramping circuitry. The same value for all gate timing capacitors is recommended. The gate capacitors must be discharged when a fault is detected to turn off the power FETs thus, larger caps slow the response time. If the gate capacitors are too large the ISL6111 may not be able to adequately protect the bus or the power FETs. The ISL6111 has internal discharge FETs to discharge the load when disabled. Upon turn-off these internal switches on each output discharge the load capacitance pulling the output to gnd. These switches are also on when ENABLE is low thus an open slot is held at the gnd level. Recommended PCB Layout Design To ensure accurate current sensing and control, the PCB traces that connect each of the current sense resistors to the ISL6111 must not carry any load current. This can be accomplished by two dedicated PCB kelvin traces directly from the sense resistors to the ISL6111, see examples of correct and incorrect layouts below in Figure 2. To reduce TABLE 1. SUPPLY NOMINAL CURRENT REGULATION LEVEL (10%) FOR EACH SUPPLY +3.3V ICR ((100 µA x RCRSET)/8.54)/RRSENSE +5.0V ICR ((100 µA x RCRSET)/12)/RRSENSE +12V ICR (100 µA x RCRSET)/0.7 -12V ICR (100 µA x RCRSET)/3.3 TABLE 2. CRTIM, VALUE 0.022F 0.1 µF1µF Nominal CR Duration 3.3ms 15ms 150ms Nominal CR Duration = 150k Ω X TIM cap value. ISL6111 |
同様の部品番号 - ISL6111CRZA |
|
同様の説明 - ISL6111CRZA |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |