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ISL59444IB-T13 データシート(PDF) 10 Page - Intersil Corporation |
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ISL59444IB-T13 データシート(HTML) 10 Page - Intersil Corporation |
10 / 11 page 10 FN7451.1 September 21, 2005 Latch State The latched control signals allow for synchronized channel switching. When LE1 is low the master control latch loads the next switching address (S0, S1), while the closed (assuming LE2 is the inverse of LE1) slave control latch maintains the current state. LE2 switching low closes the master latch (with previous assumption), loads the now open slave latch, and switches the crosspoint to the newly selected channel. Channel selection is asynchronous (changes with any control signal change) if both LE1 and LE2 are low. Power-Up Considerations The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dv/dt triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dv/dt triggered clamp imposes a maximum supply turn-on slew rate of 1V/µs. Damaging currents can flow for power supply rates-of-rise in excess of 1V/µs, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 23) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+. Limiting the Output Current No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required. PC Board Layout The frequency response of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. • The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. • Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners, use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless strip lines are used. • Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. • Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. • Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. • When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. • Minimum of 2 power supply de-coupling capacitors are recommended (1000pF, 0.01µF) as close to the devices as possible. Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. • The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk. V+ V+ V- V- V+ V- V+ V- LOGIC CONTROL GND IN0 IN1 S0 OUT EXTERNAL CIRCUITS SCHOTTKY PROTECTION V+ V- POWER GND SIGNAL LOGIC V+ SUPPLY V- SUPPLY DE-COUPLING CAPS FIGURE 23. SCHOTTKY PROTECTION CIRCUIT ISL59444 |
同様の部品番号 - ISL59444IB-T13 |
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同様の説明 - ISL59444IB-T13 |
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