データシートサーチシステム |
|
ST7DALI データシート(PDF) 60 Page - STMicroelectronics |
|
ST7DALI データシート(HTML) 60 Page - STMicroelectronics |
60 / 141 page ST7DALI 60/141 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATCSR) Read / Write Reset Value: 0x00 0000 (x0h) Bit 7 = Reserved. Bit 6 = ICF Input Capture Flag. This bit is set by hardware and cleared by software by reading the ATICR register (a read access to ATICRH or ATICRL will clear this flag). Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Bit 5 = ICIE IC Interrupt Enable. This bit is set and cleared by software. 0: Input capture interrupt disabled 1: Input capture interrupt enabled Bits 4:3 = CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter. Note 1: PWM mode and Output Compare modes are not available at this frequency. Note 2: ATICR counter may return inaccurate re- sults when read. It is therefore not recommended to use Input Capture mode at this frequency. Bit 2 = OVF Overflow Flag. This bit is set by hardware and cleared by software by reading the TCSR register. It indicates the tran- sition of the counter from FFFh to ATR value. 0: No counter overflow occurred 1: Counter overflow occurred Bit 1 = OVFIE Overflow Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset. 0: OVF interrupt disabled. 1: OVF interrupt enabled. Bit 0 = CMPIE Compare Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset. It can be used to mask the interrupt generated when the CMPF bit is set. 0: CMPF interrupt disabled. 1: CMPF interrupt enabled. COUNTER REGISTER HIGH (CNTRH) Read only Reset Value: 0000 0000 (000h) COUNTER REGISTER LOW (CNTRL) Read only Reset Value: 0000 0000 (000h) Bits 15:12 = Reserved. Bits 11:0 = CNTR[11:0] Counter Value. This 12-bit register is read by software and cleared by hardware after a reset. The counter is incre- mented continuously as soon as a counter clok is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations, LSB first. When a counter over- flow occurs, the counter restarts from the value specified in the ATR register. 76 0 0 ICF ICIE CK1 CK0 OVF OVFIE CMPIE Counter Clock Selection CK1 CK0 OFF 0 0 fLTIMER (1 ms timebase @ 8 MHz) 1) 01 fCPU 10 32 MHz 2) 11 15 8 0 000 CNTR 11 CNTR 10 CNTR9 CNTR8 70 CNTR7 CNTR6 CNTR5 CNTR4 CNTR3 CNTR2 CNTR1 CNTR0 1 |
同様の部品番号 - ST7DALI |
|
同様の説明 - ST7DALI |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |