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MSP430F5507 データシート(PDF) 85 Page - Texas Instruments |
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MSP430F5507 データシート(HTML) 85 Page - Texas Instruments |
85 / 125 page P5.3/XT2OUT 1 0 P5DIR.3 P5IN.3 EN Module X IN 1 0 Module X OUT P5OUT.3 1 0 DV SS DV CC P5REN.3 Pad Logic 1 P5DS.3 0: Low drive 1: High drive D Bus Keeper To XT2 P5SEL.2 XT2BYPASS P5SEL.3 85 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated (1) X = Don't care (2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal mode or bypass mode. (3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as general-purpose I/O. 6.11.7 Port P5 (P5.3) Input/Output With Schmitt Trigger Figure 6-8 shows the port diagram. Table 6-50 summarizes the selection of the pin functions. Figure 6-8. Port P5 (P5.3) Diagram Table 6-50. Port P5 (P5.2 and P5.3) Pin Functions PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1) P5DIR.x P5SEL.2 P5SEL.3 XT2BYPASS P5.2/XT2IN 2 P5.2 (I/O) I: 0; O: 1 0 X X XT2IN crystal mode(2) X 1 X 0 XT2IN bypass mode(2) X 1 X 1 P5.3/XT2OUT 3 P5.3 (I/O) I: 0; O: 1 0 0 X XT2OUT crystal mode(3) X 1 X 0 P5.3 (I/O)(3) X 1 0 1 |
同様の部品番号 - MSP430F5507 |
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同様の説明 - MSP430F5507 |
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