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MSP430F5509 データシート(PDF) 81 Page - Texas Instruments |
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MSP430F5509 データシート(HTML) 81 Page - Texas Instruments |
81 / 125 page P3.0/UCB0SIMO/UCB0SDA P3.1/UCB0SOMI/UCB0SCL P3.2/UCB0CLK/UCA0STE P3.3/UCA0TXD/UCA0SIMO P3.4/UCA0RXD/UCA0SOMI Direction 0: Input 1: Output P3SEL.x 1 0 P3DIR.x P3IN.x EN To module 1 0 From module P3OUT.x 1 0 DV SS DV CC P3REN.x Pad Logic 1 P3DS.x 0: Low drive 1: High drive D From module 81 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated (1) X = Don't care (2) The pin direction is controlled by the USCI module. (3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level. (4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected. 6.11.3 Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger Figure 6-4 shows the port diagram. Table 6-47 summarizes the selection of the pin functions. Figure 6-4. Port P3 (P3.0 to P3.7) Diagram Table 6-47. Port P3 (P3.0 to P3.7) Pin Functions PIN NAME (P3.x) x FUNCTION CONTROL BITS OR SIGNALS(1) P3DIR.x P3SEL.x P3.0/UCB0SIMO/UCB0SDA 0 P3.0 (I/O) I: 0; O: 1 0 UCB0SIMO/UCB0SDA(2) (3) X 1 P3.1/UCB0SOMI/UCB0SCL 1 P3.1 (I/O) I: 0; O: 1 0 UCB0SOMI/UCB0SCL (2) (3) X 1 P3.2/UCB0CLK/UCA0STE 2 P3.2 (I/O) I: 0; O: 1 0 UCB0CLK/UCA0STE(2) (4) X 1 P3.3/UCA0TXD/UCA0SIMO 3 P3.3 (I/O) I: 0; O: 1 0 UCA0TXD/UCA0SIMO(2) X 1 P3.4/UCA0RXD/UCA0SOMI 4 P3.4 (I/O) I: 0; O: 1 0 UCA0RXD/UCA0SOMI(2) X 1 |
同様の部品番号 - MSP430F5509 |
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同様の説明 - MSP430F5509 |
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