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MSP430FR6007 データシート(PDF) 55 Page - Texas Instruments |
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MSP430FR6007 データシート(HTML) 55 Page - Texas Instruments |
55 / 179 page SDA SCL t HD,DAT t SU,DAT t HD,STA t HIGH t LOW t BUF t HD,STA t SU,STA t SP t SU,STO 55 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3 – MARCH 2020 Submit Documentation Feedback Product Folder Links: MSP430FR6007 MSP430FR6005 Specifications Copyright © 2020, Texas Instruments Incorporated Table 5-21 lists the switching characteristics of the eUSCI in I2C mode. Table 5-21. eUSCI (I2C Mode) Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT feUSCI eUSCI input clock frequency Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10% 16 MHz fSCL SCL clock frequency 2.2 V, 3.0 V 0 400 kHz tHD,STA Hold time (repeated) START fSCL = 100 kHz 2.2 V, 3.0 V 4.0 µs fSCL > 100 kHz 0.6 tSU,STA Setup time for a repeated START fSCL = 100 kHz 2.2 V, 3.0 V 4.7 µs fSCL > 100 kHz 0.6 tHD,DAT Data hold time 2.2 V, 3.0 V 0 ns tSU,DAT Data setup time 2.2 V, 3.0 V 100 ns tSU,STO Setup time for STOP fSCL = 100 kHz 2.2 V, 3.0 V 4.0 µs fSCL > 100 kHz 0.6 tBUF Bus free time between a STOP and START condition fSCL = 100 kHz 4.7 us fSCL > 100 kHz 1.3 tSP Pulse duration of spikes suppressed by input filter UCGLITx = 0 2.2 V, 3.0 V 50 250 ns UCGLITx = 1 25 125 UCGLITx = 2 12.5 62.5 UCGLITx = 3 6.3 31.5 tTIMEOUT Clock low time-out UCCLTOx = 1 2.2 V, 3.0 V 27 ms UCCLTOx = 2 30 UCCLTOx = 3 33 Figure 5-16. I2C Mode Timing |
同様の部品番号 - MSP430FR6007 |
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同様の説明 - MSP430FR6007 |
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