2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

ADC Differential Input (V)

–20

–15

–10

–5

0

5

10

15

20

27

TLV197-Q1, TLV2197-Q1, TLV4197-Q1

www.ti.com

SBOS935 – APRIL 2020

Product Folder Links: TLV197-Q1 TLV2197-Q1 TLV4197-Q1

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Copyright © 2020, Texas Instruments Incorporated

Typical Applications (continued)

8.2.1.1 Design Requirements

The primary objective is to design a ±20 V, differential 4-channel multiplexed data acquisition system with lowest

distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10 kHz full-scale pure sine-wave input.

The design requirements for this block design are:

•

System supply voltage: ±15 V

•

ADC supply voltage: 3.3 V

•

ADC sampling rate: 400 kSPS

•

ADC reference voltage (REFP): 4.096 V

•

System input signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency

8.2.1.2 Detailed Design Procedure

The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for

highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 41. The circuit

is a multichannel data acquisition signal chain consisting of an input low-pass filter, multiplexer (mux), mux output

buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast

sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design

considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input

analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each

analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit

resolution and lowest distortion system. Figure 41 includes the most important specifications for each individual

analog block.

This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input

stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design

is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding

helps in the decision of an appropriate input filter and selection of a mux to meet the system settling

requirements. The next important step is the design of the attenuating analog front-end (AFE) used to level

translate the high-voltage input signal to a low-voltage ADC input when maintaining amplifier stability. The next

step is to design a digital interface to switch the mux input channels with minimum delay. The final design

challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference voltage

with low offset, drift, and noise contributions.

8.2.1.3 Application Curve

Figure 42. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TIPD151, 16-

Bit, 400 kSPS 4-Channell, Multiplexed Data Acquisition Ref erence Design for High Voltage Inputs, Low Distortion.