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SM8720AV データシート(PDF) 4 Page - Nippon Precision Circuits Inc

部品番号 SM8720AV
部品情報  3-PLL Multi-Output Clock Generator
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メーカー  NPC [Nippon Precision Circuits Inc]
ホームページ  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM8720AV データシート(HTML) 4 Page - Nippon Precision Circuits Inc

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SM8720AV
NIPPON PRECISION CIRCUITS INC.—4
AC Characteristics
fFIN = 27.0000MHz, VDD = (VDD1, VDD2, VDD3) = 3.0 ± 0.3V, VSS = (VSS1, VSS2, VSS3) = 0V,
Ta =
−40 to +85°C unless otherwise noted.
Parameter
Symbol
Pins
Conditions
Rating
Unit
min
typ
max
External input clock
frequency
fFIN
FIN
External clock input
27.0000
MHz
External clock duty cycle*1
*1. When using an external clock input, it is recommended that FIN duty cycle = 50%, clock signal amplitude = VDD level. Note that the input signal
voltage amplitude should not exceed the absolute maximum rating, otherwise the device may be damaged.
DtFIN
FIN
Ta = 25
°C, VI = 0.5VDD,
external clock input
45
50
55
%
Output clock rise time*2
*2. Measured using the circuit shown in figure 1 on the NPC standard evaluation board.
tr
REFOUT
CL = 25pF, VOL = 0.2VDD to
VOH = 0.8VDD transition
3.0
ns
All outputs excluding
REFOUT
CL = 15pF, VOL = 0.2VDD to
VOH = 0.8VDD transition
4.0
ns
Output clock fall time*2
tf
REFOUT
CL = 25pF, VOH = 0.8VDD to
VOL = 0.2VDD transition
3.0
ns
All outputs excluding
REFOUT
CL = 15pF, VOH = 0.8VDD to
VOL = 0.2VDD transition
4.0
ns
Output clock jitter
(peak-to-peak)*3,*4
*3. Measured using the circuit shown in figure 2 on the NPC standard evaluation board.
*4. Measured using master clock input on FIN with
≤80ps (peak-to-peak) jitter.
tjitter
REFOUT
Ta = 25
°C, CL = 25pF,
VO = 0.5VDD
140
200
ps
CLK1OUT,
CLK3OUT
Ta = 25
°C, CL = 15pF,
VO = 0.5VDD
220
350
ps
CLK2OUT
Ta = 25
°C, CL = 15pF,
VO = 0.5VDD
220
500
ps
Output clock duty cycle
Dt
REFOUT*2,*5
*5. Measured using master clock input on FIN with duty cycle = 50%, clock signal amplitude = VDD level.
Ta = 25
°C, CL = 25pF,
VO = 0.5VDD
45
50
55
%
All outputs excluding
REFOUT*2
Ta = 25
°C, CL = 15pF,
VO = 0.5VDD
45
50
55
%
Power-up time*2,*6
*6. The power-up time is the time from supply OFF/ON transition or enable LOW/HIGH transition until each output clock reaches its designated
frequency to within ±0.1%.
tP
All outputs excluding
REFOUT
–15
ms
Figure 1. Measurement circuit 1
Figure 2. Measurement circuit 2
Frequency &
Time Interval
Analyzer
(HP5371A)
27MHz
Oscilloscope
(Infinium
HP54845A)
Passive Probe
(HP10435A)
Active Probe
(HP1152A)
DUT
DUT:Device under test
Jitter
Measurement
System
(ASA, M1)
Oscilloscope
(HP54720D
+HP54721A)
Active Probe
(HP54701A)
DUT
DUT:Device under test
27MHz


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