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SI91872DMP-50-E3 データシート(PDF) 9 Page - Vishay Siliconix

部品番号 SI91872DMP-50-E3
部品情報  300-mA Low-Noise LDO Regulator With Error Flag and Discharge Option
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メーカー  VISHAY [Vishay Siliconix]
ホームページ  http://www.vishay.com
Logo VISHAY - Vishay Siliconix

SI91872DMP-50-E3 データシート(HTML) 9 Page - Vishay Siliconix

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Si91872
Vishay Siliconix
Document Number: 72013
S-51147—Rev. F, 20-Jun-05
www.vishay.com
9
DETAILED DESCRIPTION
The Si91872 is a low-noise, low drop-out and low quiescent
current linear voltage regulator, packaged in a small footprint
MLP33-5 package. The Si91872 can supply loads up to
300 mA. As shown in the block diagram, the circuit consists of
a bandgap reference, error amplifier, p-channel pass transistor
and feedback resistor string. Additional blocks, not shown in
the block diagram, include a precise current limiter, reverse
battery and current protection, and thermal sensor.
Thermal Overload Protection
The thermal overload protection limits the total power
dissipation and protects the device from being damaged.
When the junction temperature exceeds 150_C, the device
turns the p-channel pass transistor off.
Reverse Battery Protection
The Si91872 has a battery reverse protection circuitry that
disconnects the internal circuitry when VIN drops below the
GND voltage. There is no current drawn in such an event.
When the SD pin is hardwired to VIN, the user must connect
the SD pin to VIN via a 100-kW resistor if reverse battery
protection is desired. Hardwiring the SD pin directly to the VIN
pin is allowed when reverse battery protection is not desired.
ERROR
ERROR is an open drain output that goes low when VOUT is
less than 4% of its normal value. To obtain a logic level output,
connect a pull-up resister from ERROR to VOUT or any other
voltage equal to or less than VIN. ERROR pin is high
impedance (off) when SD pin is low.
Auto-Discharge
VOUT has an internal 100-W (typ.) discharge path to ground
when SD pin is low for the Si91872.
Stability
The circuit is stable with only a small output capacitor equal to
6 nF/mA (= 2 mF @ 300 mA). Since the bandwidth of the error
amplifier is around 1−3 MHz and the dominant pole is at the
output node, the capacitor should be capacitive in this range,
i.e., for 150-mA load current, an ESR <0.2 W is necessary.
Parasitic inductance of about 10 nH can be tolerated.
Safe Operating Area
The ability of the Si91872 to supply current is ultimately
dependent on the junction temperature of the pass device.
Junction temperature is in turn dependent on power
dissipation in the pass device, the thermal resistance of the
package and the circuit board, and the ambient temperature.
The power dissipation is defined as
PD = (VIN – VOUT) * IOUT .
Junction temperature is defined as
TJ = TA + ((PD * (RθJC + RθCA)).
To calculate the limits of performance, these equations must
be rewritten.
Allowable power dissipation is calculated using the equation
PD = (TJ − TA )/ (RθJC + RθCA)
While allowable output current is calculated using the equation
IOUT = (TJ − TA )/ (RθJC + RθCA) * (VIN – VOUT).
Ratings of the Si91872 that must be observed are
TJmax = 125 _C, TAmax = 85 _C, (VIN – VOUT)max = 5.3 V,
JC = 8 _C/W.
The value of RθCA is dependent on the PC board used. The
value of RθCA for the board used in device characterization is
approximately 46 _C/W.
Figure 1 shows the performance limits graphically for the
Si91872 mounted on the circuit board used for thermal
characterization.
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0
123
456
Figure 1. Safe Operating Area
VIN − VOUT (V)
(VIN − VOUT)MAX = 5.3 V
TA = 50_C
TA = 85_C
TA = 70_C
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and
Package Reliability represent a composite of all qualified locations.
For related documents such as package/tape drawings, part marking, and reliability data, see
http://www.vishay.com/ppg?72013.


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