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XT
April 1999
4.5.99
4
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Table 4: Byte 0 - SDRAM Control Register 0
REGISTER
BIT
CLOCK
OUTPUT
DESCRIPTION
OUTPUT PIN
(FS6050)
OUTPUT PIN
(FS6051)
OUTPUT PIN
(FS6053)
OUTPUT PIN
(FS6054)
7
SDRAM_7
On (1) / Off (0)
Pin 18
-
Pin 11
Pin 11
6
SDRAM_6
On (1) / Off (0)
Pin 17
-
Pin 10
Pin 10
5
SDRAM_5
On (1) / Off (0)
Pin 14
-
-
-
4
SDRAM_4
On (1) / Off (0)
Pin 13
-
-
-
3
SDRAM_3
On (1) / Off (0)
Pin 9
Pin 7
Pin 7
Pin 7
2
SDRAM_2
On (1) / Off (0)
Pin 8
Pin 6
Pin 6
Pin 6
1
SDRAM_1
On (1) / Off (0)
Pin 5
Pin 3
Pin 3
Pin 3
0
SDRAM_0
On (1) / Off (0)
Pin 4
Pin 2
Pin 2
Pin 2
Table 5: Byte 1 - SDRAM Control Register 1
REGISTER
BIT
CLOCK
OUTPUT
DESCRIPTION
OUTPUT PIN
(FS6050)
OUTPUT PIN
(FS6051)
OUTPUT PIN
(FS6053)
OUTPUT PIN
(FS6054)
15
SDRAM_15
On (1) / Off (0)
Pin 45
Pin 27
Pin 27
Pin 27
14
SDRAM_14
On (1) / Off (0)
Pin 44
Pin 26
Pin 26
Pin 26
13
SDRAM_13
On (1) / Off (0)
Pin 41
Pin 23
Pin 23
Pin 23
12
SDRAM_12
On (1) / Off (0)
Pin 40
Pin 22
Pin 22
Pin 22
11
SDRAM_11
On (1) / Off (0)
Pin 36
-
-
-
10
SDRAM_10
On (1) / Off (0)
Pin 35
-
-
-
9
SDRAM_9
On (1) / Off (0)
Pin 32
-
Pin 19
Pin 19
8
SDRAM_8
On (1) / Off (0)
Pin 31
-
Pin 18
Pin 18
Table 6: Byte 2 - SDRAM Control Register 2
REGISTER
BIT
CLOCK
OUTPUT
DESCRIPTION
OUTPUT PIN
(FS6050)
OUTPUT PIN
(FS6051)
OUTPUT PIN
(FS6053)
OUTPUT PIN
(FS6054)
23
SDRAM_17
On (1) / Off (0)
Pin 28
Pin 18
-
Pin 17
22
SDRAM_16
On (1) / Off (0)
Pin 21
Pin 11
Pin 12
Pin 12
21
Reserved (set to 0)
-
-
-
-
20
Reserved (set to 0)
-
-
-
-
19
Reserved (set to 0)
-
-
-
-
18
Reserved (set to 0)
-
-
-
-
17
Reserved (set to 0)
-
-
-
-
16
Reserved (set to 0)
-
-
-
-