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TLE75620-EST データシート(PDF) 26 Page - Infineon Technologies AG |
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TLE75620-EST データシート(HTML) 26 Page - Infineon Technologies AG |
26 / 81 page Datasheet 26 Rev. 1.0 2017-11-23 TLE75620-EST SPIDER+ 12V Power Supply in Table 6. Figure 15 sketches the undervoltage behavior (the “VS - VDS” line refers to a channel which is programmed to be ON). Figure 15 VS Undervoltage Behavior 6.2.2 Low Operating Power on VDD When VDD supply voltage is in the range indicated by VDD(LOP), the bit LOPVDD is set to “1”. As soon as VDD > VDD(LOP) the bit LOPVDD is set to “0” after the first Standard Diagnosis readout. If VDD supply voltage is not present, a voltage applied to pins CSN or SO can supply the internal logic (not recommended in normal operation due to internal design limitations). Supply_UVRVS.emf t VS(OP) VS(UV) 1 UVRVS 0 1 t VS(HYS) t VS - VDS VS |
同様の部品番号 - TLE75620-EST |
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同様の説明 - TLE75620-EST |
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