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SX-A Family FPGAs
v5.1
2-19
tINYH
Input Data Pad to Y High 5 V PCI
0.5
0.6
0.7
0.9
ns
tINYL
Input Data Pad to Y Low 5 V PCI
0.8
0.9
1.1
1.5
ns
tINYH
Input Data Pad to Y High 5 V TTL
0.5
0.6
0.7
0.9
ns
tINYL
Input Data Pad to Y Low 5 V TTL
0.8
0.9
1.1
1.5
ns
Input Module Predicted Routing Delays2
tIRD1
FO = 1 Routing Delay
0.3
0.3
0.4
0.6
ns
tIRD2
FO = 2 Routing Delay
0.5
0.5
0.6
0.8
ns
tIRD3
FO = 3 Routing Delay
0.6
0.7
0.8
1.1
ns
tIRD4
FO = 4 Routing Delay
0.8
0.9
1
1.4
ns
tIRD8
FO = 8 Routing Delay
1.4
1.5
1.8
2.5
ns
tIRD12
FO = 12 Routing Delay
2
2.2
2.6
3.6
ns
Table 2-14 • A54SX08A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions, VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
Parameter
Description
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max.
Min.
Max.
Min. Max.
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
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