TS3405 datasheet(8/10 Pages) TSC

部品番号	TS3405

部品情報	Single Synchronous Buck PWM Controller

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メーカー	TSC [Taiwan Semiconductor Company, Ltd]

ホームページ	http://www.taiwansemi.com

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Application Guidelines (continued)

Output Inductor

The output inductor is selected to meet the output

voltage ripple requirements and minimize the converter’s

response time to the load transient. The inductor value

determines the converter’s ripple current and the ripple

voltage is a function of the ripple current. The ripple

voltage and current are approximated by the following

equations:

∆I = (Vin - Vout) / FS x L x (Vout / Vin)

∆Vout = ∆I x ESR

Increasing the value of inductance reduces the ripple

current and voltage. However, the large inductance

values reduce the converter’s response time to a load

transient. One of the parameters limiting the converter’s

response to a load transient is the time required to

change the inductor current. Given a sufficiently fast

control loop design, the TS3405 will provide either 0% or

100% duty cycle in response to a load transient. The

response time is the time required to slew the inductor

current from an initial current value to the transient

current level. During this interval the difference between

the inductor current and the transient current level must

be supplied by the output capacitor to minimizing the

response time can minimize the output capacitance

required.

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

tRISE = (L x ITRAN) / (Vin - Vout)

tFALL = (L x ITRAN) / Vout

where:

ITRAN is the transient load current step

tRISE is the response time to the application of load

tFALL is the response time to the removal of load

the worst case response time can be either at the

equations at the minimum and maximum output levels for

the worst case response time.

Feedback Compensation

Fig. 6 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(Vout) is regulated to the reference voltage level. The

error amplifier (Error Amp) output (VE/A) is compared

with the oscillator (OSC) triangular wave to provide a

pulse-width modulated (PWM) wave with a amplitude of

Vin at the Phase node. The PWM wave is smoothed by

the output filter (Lo and Co).

The modulator transfer function is the small-signal

transfer function of Vout / VE/A. This function is dominated

by a DC Gain and the output filter (Lo and Co), with a

double pole break frequency at FLC and a zero at FESR.

The DC Gain of the modulator is simply the imput voltage

(Vin) divided by the peak-to-peak oscillator voltage VOSC.

Modulator Break Frequency Equations

FLC = 1 / 2π x √ Lo x Co

FESR = 1 / 2π x ESR x Co

Compensation Break Frequency Equations

FZ = 1 / 2π x R2 x C1

FP1 = 1 / 2π x R2 x [(C1 x C2) / (C1 + C2)]

FZ1 = 1 / 2π x (R1 + R3) x C3

FP2 = 1 / 2π x R3 x C3

The compensation network consists of the error amplifier

(internal to the TS3405) and the impedance networks

ZIN and ZFB. The goal of the compensation network is

to provide a closed loop transfer function with the

highest 0dB crossing frequency (f0dB) and adequate

phase margin. Phase margin is the difference between

the closed loop phase at f0dB and 180 degrees.

FIGURE 6、Voltage-mode buck converter

compensation design.

DETAILED COMPENSATION COMPONENT

FB

COMP

Reference

Vout

+

ZFD

ZIN

Lout

Driver

Vin

Phase

ESR

Vout

TS3405

_

+

_

Co

ZIN

C3

ZFD

C2

C1

R3

R1

R2

PWM

OSC

Error AMP

VE/A

Reference

OSC

TS3405

8-10

2003/12 rev. A

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