TC90A66F

2001-06-07

11

Pin Number

Pin Name

Function

99

RHREF

PLL phase compare output pin for main picture.

The HREF signal obtained by the I/N divider circuit or the phase comparison result of RHD signal. This

signal is used to control the external VCO voltage.

100

RCK

Read clock input pin. It is composing 5 V interface.

Inputs from the external PLL circuit.

Inputs 2400 fH for both 4M and 2M memory.

102

RHD

Horizontal sync signal input pin for main picture (read). Inputs horizontal sync signal from VCD for main

picture. It is composing 5 V interface (negative polarity input). For negative polarity input, set sub

address [28H: RHINV] to non-inversion (L).

103

RVD

Vertical sync signal input pin for main picture (read). Inputs vertical sync signal from VCD for main

picture. It is composing 5 V interface (negative polarity input). For negative polarity input, set sub

address [28H: RVINV] to non-inversion (L).

104

YS

signal is High, displays sub picture.

105

KAYS

Wallpaper YS signal output.

106

HYOJUN

Standard/non-standard signal output pin [standard (L)/non-standard (H)]

107

PWRST

System reset input pin. When low input, it carries out the reset.

At least 1 V is required as reset duration.

110

IICNR

I

When set to off (connect to GND), data are written to register directly.

111

SADSEL

Sub address of main/sub picture switching pin. [main (H)/sub (L)]

Normally, set to L (enables sub addresses 00h to 7Fh).

112

SACN

I

114

SCL

I

115

SDA

I

It is composing 5 V interface.

136

YOUT

138

IOUT

140

QOUT

141 to 142

VB2-1

Bias pin for DAC.

Connect a 0.1

µF bypass capacitor between the pins and GND.

143

VREF

DAC reference voltage input pin.

Reference voltage is 2.3 V typical.

144

ADBIAS

Bias pin for ADC.

Connect a 0.1

µF bypass capacitor between the pin and AGND.