IS25WP032D-JELE datasheet(79/118 Pages) ISSI

部品番号	IS25WP032D-JELE

部品情報	SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

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IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

79

Rev. A12

08/04/2020

8.34 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE RESET

The Software Reset operation is used as a system reset that puts the device in normal operating mode. During the

Reset operation, the value of volatile registers will default back to the value in the corresponding non-volatile

register. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). The operation

requires the Reset-Enable command followed by the Reset command. Any command other than the Reset

command after the Reset-Enable command will disable the Reset-Enable.

Execute the CE# pin low  sends the Reset-Enable command (66h), and drives CE# high. Next, the host drives

CE# low again, sends the Reset command (99h), and pulls CE# high.

Only if the RESET# pin is enabled, Hardware Reset function is available.

For the device with HOLD#/RESET#, the RESET# pin will be solely applicable in SPI mode and when the QE bit =

“0”. For the device with dedicated RESET# (Dedicated RESET# Disable bit is “0” in Function Register), the RESET#

pin is always applicable regardless of the QE bit value in Status Register and HOLD#/RESET# selection bit (P7) in

Read Register in SPI/QPI mode.

In order to activate Hardware Reset, the RESET# pin (or ball) must be driven low for a minimum period of tRESET

(100ns). Drive RESET# low for a minimum period of tRESET will interrupt any on-going internal and external

operations, release the device from deep power down mode1, disable all input signals, force the output pin enter a

state of high impedance, and reset all the read parameters.

The required wait time after activating a HW Reset before the device will accept another instruction is tHWRST of

35us.

The Software/Hardware Reset during an active Program or Erase operation aborts the operation, which can result

in corrupting or losing the data of the targeted address range. Depending on the prior operation, the reset timing

may vary. Recovery from a Write operation will require more latency than recovery from other operations.

Note1: The Status and Function Registers remain unaffected.

Figure 8.58 Software Reset Enable and Software Reset Sequence In SPI Mode (RSTEN, 66h + RST, 99h)

Instruction = 66h

CE#

SCK

SI

0

1

Mode 3

Mode 0

2

3

4

5

6

7

Instruction = 99h

8

9

10

11

12

13

14

15

SO

High Impedance

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