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NTP53X2 データシート(PDF) 32 Page - NXP Semiconductors |
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NTP53X2 データシート(HTML) 32 Page - NXP Semiconductors |
32 / 133 page NXP Semiconductors NTP53x2 NTAG 5 link - NFC Forum-compliant I2C bridge NTP53x2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 3.3 — 3 July 2020 COMPANY PUBLIC 544533 32 / 133 Table 37. Configuration Definition (CONFIG_0) Bit Name Value Description 0b SRAM copy on POR disabled (default) 7 SRAM_COPY_EN 1b SRAM copy on POR enabled 6 to 4 RFU 0b 00b 3 01b RFU 10b Energy harvesting optimized for low field strength (default) 2 EH_MODE 11b Energy harvesting optimized for high field strength 0b NFC Write access to all session register (default) 1 LOCK_SESSION_REG 1b No NFC write access to session registers A3h to A7h 0b Normal Operation Mode (Default) 0 AUTO_STANDBY_MODE_EN 1b IC enters standby mode after boot if there is no RF field present automatically. Table 38. Configuration Definition (CONFIG_1) Bit Name Value Description 0b In energy harvesting use case, ARBITER_MODE needs to be set with session registers after startup (default) 7 EH_ARBITER_MODE_EN 1b ARBITER_MODE is set automatically in any case after startup 6 RFU 0b 00b I2C slave (default) 5 01b I2C master only for NTP5332 10b GPIO/PWM 4 USE_CASE_CONF 11b All host interface functionality disabled and pads are in 3-state mode 00b Normal Mode (default) 3 01b SRAM mirror mode 10b SRAM passes through mode 2 ARBITER_MODE 11b SRAM PHDC mode 0b SRAM is not accessible (default) 1 SRAM_ENABLE 1b SRAM is available (when VCC supplied) 0b Data transfer direction is I2C to NFC (default) 0 PT_TRANSFER_DIR 1b Data transfer direction is NFC to I2C |
同様の部品番号 - NTP53X2 |
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同様の説明 - NTP53X2 |
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