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BQ79600-Q1 データシート(PDF) 13 Page - Texas Instruments |
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BQ79600-Q1 データシート(HTML) 13 Page - Texas Instruments |
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13 / 71 page  7.3.1.4 Digital Reset Digital reset is when digital core of the device in reset mode. It is not a power mode. Once device comes out of digital reset, [DRST] bit is set to '1', registers that are not included in NVM are set to RESET VALUE, registers included in NVM would be NVM program value. There are several conditions in which the device will go through a digital reset: • A WAKE ping is received. • The CONTROL1 [SOFT_RESET] = 1 command is sent in ACTIVE mode. • Power supply faults. DVDD UV or CVDD UV is detected. • A HFO or LFO watchdog fault will reset the digital. 7.3.1.5 Power Mode in BMS System It is recommended to follow the power state combinations below to save system level power. Table 7-3. Power Mode Combination Summary STACK MONITORING IC BQ79600-Q1 COMMENT ACTIVE ACTIVE Recommended SLEEP SLEEP Recommended SLEEP SHUTDOWN Recommended SHUTDOWN SHUTDOWN Recommended Other combinations Not recommended 7.3.1.6 Power Supply This section provides an overview of each supplies for both user cases: without using Reverse Wakeup and with using Reverse Wakeup. See the Section 7.3.6 for diagnostic control and fault detection on the power supplies block. Table 7-4. Power Supply Summary NAME W/O REVERSE WAKEUP USER CASE W/ REVERSE WAKEUP USER CASE VIO This supply is powered by regulated 3.3V or 5V from SBC (PMIC), it powers UART/SPI interface pins. BAT This supply is powered by regulated 5V from SBC (PMIC). This supply is powered by unregulated 12V battery. AVAOREF This supply is generated from VBAT. It is always on if VBAT exists. It powers REFSYS and Power mode control block. AVDDREF This supply is derived from AVAOREF. AVDDREF and AVAOREF are connected by a switch, the switch is open in SHUTDOWN mode. DVDD This supply is generated by the internal DVDD LDO. It is the supply for the digital circuits. It takes the input voltage from CVDD and generates a nominal 1.8V. It will not be used to power any external circuit. CVDD This supply is powered by regulated 5V from SBC(PMIC). It is the supply for daisy chain interface. This supply is generated by the internal CVDD LDO. It is the supply for the daisy chain interface (or vertical interface, VIF). It takes the input voltage from VBAT and generates a nominal 5V. It will not be used to power any external circuit. 7.3.1.7 Shutdown Power Mode Transition Example www.ti.com BQ79600-Q1 SLUSDS1A – NOVEMBER 2019 – REVISED AUGUST 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: BQ79600-Q1 |
同様の部品番号 - BQ79600-Q1_V01 |
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同様の説明 - BQ79600-Q1_V01 |
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