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DRV8353M データシート(PDF) 5 Page - Texas Instruments |
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DRV8353M データシート(HTML) 5 Page - Texas Instruments |
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5 / 76 page  7 Absolute Maximum Ratings at TA = –55°C to +125°C (unless otherwise noted)(1) MIN MAX UNIT GATE DRIVER Power supply pin voltage (VM) –0.3 80 V Voltage differential between ground pins (AGND, BGND, DGND, PGND) –0.3 0.3 V MOSFET drain sense pin voltage (VDRAIN) –0.3 102 V MOSFET drain sense pin voltage slew rate (VDRAIN) 0 2 V/µs Charge pump pin voltage (CPH, VCP) –0.3 VVDRAIN + 16 V Charge-pump negative-switching pin voltage (CPL) –0.3 VVDRAIN V Low-side gate drive regulator pin voltage (VGLS) –0.3 18 V Internal logic regulator pin voltage (DVDD) –0.3 5.75 V Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS) –0.3 5.75 V Continuous high-side gate drive pin voltage (GHx) –5(2) VVCP + 0.3 V Transient 200-ns high-side gate drive pin voltage (GHx) –10 VVCP + 0.3 V High-side gate drive pin voltage with respect to SHx (GHx) –0.3 16 V Continuous high-side source sense pin voltage (SHx) –5(2) 102 V Continuous high-side source sense pin voltage (SHx) –5(2) VVDRAIN + 5 V Transient 200-ns high-side source sense pin voltage (SHx) –10 VVDRAIN + 10 V Continuous low-side gate drive pin voltage (GLx) –1.0 VVGLS + 0.3 V Transient 200-ns low-side gate drive pin voltage (GLx) –5.0 VVGLS + 0.3 V Gate drive pin source current (GHx, GLx) Internally limited Internally limited A Gate drive pin sink current (GHx, GLx) Internally limited Internally limited A Continuous low-side source sense pin voltage (SLx) –1 1 V Transient 200-ns low-side source sense pin voltage (SLx) –5 5 V Continuous shunt amplifier input pin voltage (SNx, SPx) –1 1 V Transient 200-ns shunt amplifier input pin voltage (SNx, SPx) –5 5 V Reference input pin voltage (VREF) –0.3 5.75 V Shunt amplifier output pin voltage (SOx) –0.3 VVREF + 0.3 V DRV8353M Ambient temperature, TA –55 125 °C Junction temperature, TJ –55 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) VDRAIN pin voltage with respect to high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to 102 V maximum. This will limit the GHx and SHx pin negative voltage capability when VDRAIN is greater than 92 V. www.ti.com DRV8353M SLVSFO2 – JULY 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DRV8353M |
同様の部品番号 - DRV8353M |
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