9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

General application guidelines and hints for LVDS drivers and receivers may be found in the LVDS application

notes and design guides.

9.2 Typical Application

Figure 9-1. Balanced System Point-to-Point Application

9.2.1 Design Requirements

When using LVDS devices, it is important to remember to specify controlled impedance PCB traces. All

components of the transmission media must have a matched differential impedance of 100 Ω. They must not

introduce major impedance discontinuities.

9.2.2 Detailed Design Procedure

9.2.2.1 Power Decoupling Recommendations

Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)

0.1 μF and 0.01 μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the

device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple

vias should be used to connect the decoupling capacitors to the power planes. A 10 μF (35 V) or greater solid

tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply

and ground.

9.2.2.2 Termination

Use a termination resistor which best matches the differential impedance or your transmission line. The resistor

should be between 90 Ω and 110 Ω. Remember that the current mode outputs need the termination resistor to

generate the differential voltage. LVDS will not work correctly without resistor termination. Typically, connecting a

single resistor across the pair at the receiver end will suffice.

Surface mount 1% resistors are the best. PCB stubs, component lead, and the distance from the termination to

the receiver inputs should be minimized. The distance between the termination resistor and the receiver should

be < 10 mm (12 mm MAX).

9.2.2.3 Input Failsafe Biasing

External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe

under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor

and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors

should be in the 5 kΩ to 15 kΩ range to minimize loading and waveform distortion to the driver. The common-

mode bias point ideally should be set to approximately 1.2 V to be compatible with the internal circuitry. Please

refer to application note AN-1194, “Failsafe Biasing of LVDS Interfaces” (SNLA051)for more information.

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DS90LV028A-Q1

SNLS672 – AUGUST 2020

Copyright © 2020 Texas Instruments Incorporated

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